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Added Verilog support for "`default_nettype none"

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Clifford Wolf 2014-02-17 14:28:52 +01:00
parent 0851c2b6ea
commit 02e6f2c5be
8 changed files with 31 additions and 8 deletions
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frontends/verilog/parser.y
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@ -53,6 +53,7 @@ namespace VERILOG_FRONTEND {
struct AstNode *current_ast, *current_ast_mod;
int current_function_or_task_port_id;
std::vector<char> case_type_stack;
bool default_nettype_wire;
}
static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)