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Added Verilog support for "`default_nettype none"

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This commit is contained in:
Clifford Wolf 2014-02-17 14:28:52 +01:00
parent 0851c2b6ea
commit 02e6f2c5be
8 changed files with 31 additions and 8 deletions
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12
frontends/verilog/lexer.l
View file

@ -81,6 +81,18 @@ namespace VERILOG_FRONTEND {
"`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
"`default_nettype"[ \t]+[^ \t\r\n/]+ {
char *p = yytext;
while (*p != 0 && *p != ' ' && *p != '\t') p++;
while (*p == ' ' || *p == '\t') p++;
if (!strcmp(p, "none"))
VERILOG_FRONTEND::default_nettype_wire = false;
else if (!strcmp(p, "wire"))
VERILOG_FRONTEND::default_nettype_wire = true;
else
frontend_verilog_yyerror("Unsupported default nettype: %s", p);
}
"`"[a-zA-Z_$][a-zA-Z0-9_$]* {
frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
}

1
frontends/verilog/parser.y
View file

@ -53,6 +53,7 @@ namespace VERILOG_FRONTEND {
struct AstNode *current_ast, *current_ast_mod;
int current_function_or_task_port_id;
std::vector<char> case_type_stack;
bool default_nettype_wire;
}
static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)

1
frontends/verilog/preproc.cc
View file

@ -373,7 +373,6 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
}
if (tok == "`timescale") {
std::string name;
skip_spaces();
while (!tok.empty() && tok != "\n")
tok = next_token(true);

3
frontends/verilog/verilog_frontend.cc
View file

@ -256,6 +256,7 @@ struct VerilogFrontend : public Frontend {
AST::get_line_num = &frontend_verilog_yyget_lineno;
current_ast = new AST::AstNode(AST::AST_DESIGN);
default_nettype_wire = true;
FILE *fp = f;
std::string code_after_preproc;
@ -279,7 +280,7 @@ struct VerilogFrontend : public Frontend {
child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
}
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer);
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);
if (!flag_nopp)
fclose(fp);

3
frontends/verilog/verilog_frontend.h
View file

@ -42,6 +42,9 @@ namespace VERILOG_FRONTEND
// this function converts a Verilog constant to an AST_CONSTANT node
AST::AstNode *const2ast(std::string code, char case_type = 0);
// state of `default_nettype
extern bool default_nettype_wire;
}
// the pre-processor