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ID(\\.*) -> ID(.*)

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This commit is contained in:
Eddie Hung 2019-08-15 10:25:54 -07:00
parent 467c34eff0
commit 02dead2e60
25 changed files with 766 additions and 766 deletions
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18
passes/techmap/zinit.cc
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@ -62,12 +62,12 @@ struct ZinitPass : public Pass {
for (auto wire : module->selected_wires())
{
if (wire->attributes.count(ID(\\init)) == 0)
if (wire->attributes.count(ID(init)) == 0)
continue;
SigSpec wirebits = sigmap(wire);
Const initval = wire->attributes.at(ID(\\init));
wire->attributes.erase(ID(\\init));
Const initval = wire->attributes.at(ID(init));
wire->attributes.erase(ID(init));
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
{
@ -103,8 +103,8 @@ struct ZinitPass : public Pass {
if (!dff_types.count(cell->type))
continue;
SigSpec sig_d = sigmap(cell->getPort(ID(\\D)));
SigSpec sig_q = sigmap(cell->getPort(ID(\\Q)));
SigSpec sig_d = sigmap(cell->getPort(ID(D)));
SigSpec sig_q = sigmap(cell->getPort(ID(Q)));
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
continue;
@ -120,14 +120,14 @@ struct ZinitPass : public Pass {
}
Wire *initwire = module->addWire(NEW_ID, GetSize(initval));
initwire->attributes[ID(\\init)] = initval;
initwire->attributes[ID(init)] = initval;
for (int i = 0; i < GetSize(initwire); i++)
if (initval.bits.at(i) == State::S1)
{
sig_d[i] = module->NotGate(NEW_ID, sig_d[i]);
module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]);
initwire->attributes[ID(\\init)].bits.at(i) = State::S0;
initwire->attributes[ID(init)].bits.at(i) = State::S0;
}
else
{
@ -137,8 +137,8 @@ struct ZinitPass : public Pass {
log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
log_signal(sig_q), log_signal(initval));
cell->setPort(ID(\\D), sig_d);
cell->setPort(ID(\\Q), initwire);
cell->setPort(ID(D), sig_d);
cell->setPort(ID(Q), initwire);
}
for (auto &it : initbits)