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https://github.com/YosysHQ/yosys
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ID(\\.*) -> ID(.*)
This commit is contained in:
Eddie Hung
parent
467c34eff0
commit
02dead2e60
25 changed files with 766 additions and 766 deletions
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@ -145,8 +145,8 @@ struct TechmapWorker
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record.wire = it.second;
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record.value = it.second;
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result[p].push_back(record);
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it.second->attributes[ID(\\keep)] = RTLIL::Const(1);
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it.second->attributes[ID(\\_techmap_special_)] = RTLIL::Const(1);
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it.second->attributes[ID(keep)] = RTLIL::Const(1);
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it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
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}
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}
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@ -175,11 +175,11 @@ struct TechmapWorker
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}
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std::string orig_cell_name;
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pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(\\src));
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pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
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if (!flatten_mode) {
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for (auto &it : tpl->cells_)
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if (it.first == ID(\\_TECHMAP_REPLACE_)) {
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if (it.first == ID(_TECHMAP_REPLACE_)) {
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orig_cell_name = cell->name.str();
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module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
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break;
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@ -197,8 +197,8 @@ struct TechmapWorker
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m->start_offset = it.second->start_offset;
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m->size = it.second->size;
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m->attributes = it.second->attributes;
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if (m->attributes.count(ID(\\src)))
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m->add_strpool_attribute(ID(\\src), extra_src_attrs);
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if (m->attributes.count(ID(src)))
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m->add_strpool_attribute(ID(src), extra_src_attrs);
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module->memories[m->name] = m;
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memory_renames[it.first] = m->name;
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design->select(module, m);
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@ -215,10 +215,10 @@ struct TechmapWorker
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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if (it.second->get_bool_attribute(ID(\\_techmap_special_)))
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if (it.second->get_bool_attribute(ID(_techmap_special_)))
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w->attributes.clear();
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if (w->attributes.count(ID(\\src)))
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w->add_strpool_attribute(ID(\\src), extra_src_attrs);
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if (w->attributes.count(ID(src)))
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w->add_strpool_attribute(ID(src), extra_src_attrs);
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design->select(module, w);
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}
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@ -320,7 +320,7 @@ struct TechmapWorker
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}
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for (auto &attr : w->attributes) {
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if (attr.first == ID(\\src))
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if (attr.first == ID(src))
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continue;
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module->connect(extra_connect);
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break;
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@ -331,7 +331,7 @@ struct TechmapWorker
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for (auto &it : tpl->cells_)
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{
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IdString c_name = it.second->name.str();
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bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(\\_TECHMAP_REPLACE_));
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bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(_TECHMAP_REPLACE_));
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if (techmap_replace_cell)
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c_name = orig_cell_name;
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@ -350,19 +350,19 @@ struct TechmapWorker
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}
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if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
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IdString memid = c->getParam(ID(\\MEMID)).decode_string();
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IdString memid = c->getParam(ID(MEMID)).decode_string();
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log_assert(memory_renames.count(memid) != 0);
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c->setParam(ID(\\MEMID), Const(memory_renames[memid].str()));
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c->setParam(ID(MEMID), Const(memory_renames[memid].str()));
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}
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if (c->type == ID($mem)) {
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IdString memid = c->getParam(ID(\\MEMID)).decode_string();
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IdString memid = c->getParam(ID(MEMID)).decode_string();
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apply_prefix(cell->name, memid);
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c->setParam(ID(\\MEMID), Const(memid.c_str()));
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c->setParam(ID(MEMID), Const(memid.c_str()));
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}
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if (c->attributes.count(ID(\\src)))
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c->add_strpool_attribute(ID(\\src), extra_src_attrs);
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if (c->attributes.count(ID(src)))
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c->add_strpool_attribute(ID(src), extra_src_attrs);
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if (techmap_replace_cell)
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for (auto attr : cell->attributes)
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@ -416,9 +416,9 @@ struct TechmapWorker
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}
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if (flatten_mode) {
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bool keepit = cell->get_bool_attribute(ID(\\keep_hierarchy));
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bool keepit = cell->get_bool_attribute(ID(keep_hierarchy));
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for (auto &tpl_name : celltypeMap.at(cell_type))
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if (map->modules_[tpl_name]->get_bool_attribute(ID(\\keep_hierarchy)))
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if (map->modules_[tpl_name]->get_bool_attribute(ID(keep_hierarchy)))
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keepit = true;
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if (keepit) {
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if (!flatten_keep_list[cell]) {
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@ -484,13 +484,13 @@ struct TechmapWorker
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{
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std::string extmapper_name;
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if (tpl->get_bool_attribute(ID(\\techmap_simplemap)))
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if (tpl->get_bool_attribute(ID(techmap_simplemap)))
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extmapper_name = "simplemap";
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if (tpl->get_bool_attribute(ID(\\techmap_maccmap)))
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if (tpl->get_bool_attribute(ID(techmap_maccmap)))
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extmapper_name = "maccmap";
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if (tpl->attributes.count(ID(\\techmap_wrap)))
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if (tpl->attributes.count(ID(techmap_wrap)))
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extmapper_name = "wrap";
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if (!extmapper_name.empty())
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@ -505,7 +505,7 @@ struct TechmapWorker
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m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
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if (extmapper_name == "wrap")
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m_name += ":" + sha1(tpl->attributes.at(ID(\\techmap_wrap)).decode_string());
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m_name += ":" + sha1(tpl->attributes.at(ID(techmap_wrap)).decode_string());
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RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
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RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
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@ -520,7 +520,7 @@ struct TechmapWorker
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int port_counter = 1;
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for (auto &c : extmapper_cell->connections_) {
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RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
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if (w->name.in(ID(\\Y), ID(\\Q)))
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if (w->name.in(ID(Y), ID(Q)))
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w->port_output = true;
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else
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w->port_input = true;
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@ -548,7 +548,7 @@ struct TechmapWorker
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}
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if (extmapper_name == "wrap") {
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std::string cmd_string = tpl->attributes.at(ID(\\techmap_wrap)).decode_string();
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std::string cmd_string = tpl->attributes.at(ID(techmap_wrap)).decode_string();
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log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
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mkdebug.on();
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Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
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@ -616,8 +616,8 @@ struct TechmapWorker
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continue;
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}
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if (tpl->avail_parameters.count(ID(\\_TECHMAP_CELLTYPE_)) != 0)
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parameters[ID(\\_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
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if (tpl->avail_parameters.count(ID(_TECHMAP_CELLTYPE_)) != 0)
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parameters[ID(_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
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for (auto conn : cell->connections()) {
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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@ -656,8 +656,8 @@ struct TechmapWorker
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bits = i;
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// Increment index by one to get number of bits
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bits++;
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if (tpl->avail_parameters.count(ID(\\_TECHMAP_BITS_CONNMAP_)))
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parameters[ID(\\_TECHMAP_BITS_CONNMAP_)] = bits;
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if (tpl->avail_parameters.count(ID(_TECHMAP_BITS_CONNMAP_)))
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parameters[ID(_TECHMAP_BITS_CONNMAP_)] = bits;
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for (auto conn : cell->connections())
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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@ -1136,8 +1136,8 @@ struct TechmapPass : public Pass {
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std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
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for (auto &it : map->modules_) {
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if (it.second->attributes.count(ID(\\techmap_celltype)) && !it.second->attributes.at(ID(\\techmap_celltype)).bits.empty()) {
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char *p = strdup(it.second->attributes.at(ID(\\techmap_celltype)).decode_string().c_str());
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if (it.second->attributes.count(ID(techmap_celltype)) && !it.second->attributes.at(ID(techmap_celltype)).bits.empty()) {
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char *p = strdup(it.second->attributes.at(ID(techmap_celltype)).decode_string().c_str());
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for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
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celltypeMap[RTLIL::escape_id(q)].insert(it.first);
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free(p);
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@ -1222,7 +1222,7 @@ struct FlattenPass : public Pass {
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RTLIL::Module *top_mod = NULL;
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if (design->full_selection())
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for (auto mod : design->modules())
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if (mod->get_bool_attribute(ID(\\top)))
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if (mod->get_bool_attribute(ID(top)))
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top_mod = mod;
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std::set<RTLIL::Cell*> handled_cells;
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