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https://github.com/YosysHQ/yosys
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ID(\\.*) -> ID(.*)
This commit is contained in:
Eddie Hung
parent
467c34eff0
commit
02dead2e60
25 changed files with 766 additions and 766 deletions
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@ -73,22 +73,22 @@ struct ShregmapTechGreenpak4 : ShregmapTech
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bool fixup(Cell *cell, dict<int, SigBit> &taps)
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{
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auto D = cell->getPort(ID(\\D));
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auto C = cell->getPort(ID(\\C));
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auto D = cell->getPort(ID(D));
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auto C = cell->getPort(ID(C));
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auto newcell = cell->module->addCell(NEW_ID, ID(\\GP_SHREG));
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newcell->setPort(ID(\\nRST), State::S1);
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newcell->setPort(ID(\\CLK), C);
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newcell->setPort(ID(\\IN), D);
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auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG));
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newcell->setPort(ID(nRST), State::S1);
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newcell->setPort(ID(CLK), C);
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newcell->setPort(ID(IN), D);
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int i = 0;
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for (auto tap : taps) {
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newcell->setPort(i ? ID(\\OUTB) : ID(\\OUTA), tap.second);
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newcell->setParam(i ? ID(\\OUTB_TAP) : ID(\\OUTA_TAP), tap.first + 1);
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newcell->setPort(i ? ID(OUTB) : ID(OUTA), tap.second);
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newcell->setParam(i ? ID(OUTB_TAP) : ID(OUTA_TAP), tap.first + 1);
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i++;
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}
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cell->setParam(ID(\\OUTA_INVERT), 0);
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cell->setParam(ID(OUTA_INVERT), 0);
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return false;
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}
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};
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@ -105,18 +105,18 @@ struct ShregmapTechXilinx7 : ShregmapTech
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for (const auto &i : module->cells_) {
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auto cell = i.second;
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if (cell->type == ID($shiftx)) {
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if (cell->getParam(ID(\\Y_WIDTH)) != 1) continue;
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if (cell->getParam(ID(Y_WIDTH)) != 1) continue;
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int j = 0;
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for (auto bit : sigmap(cell->getPort(ID(\\A))))
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for (auto bit : sigmap(cell->getPort(ID(A))))
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sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
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log_assert(j == cell->getParam(ID(\\A_WIDTH)).as_int());
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log_assert(j == cell->getParam(ID(A_WIDTH)).as_int());
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}
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else if (cell->type == ID($mux)) {
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int j = 0;
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for (auto bit : sigmap(cell->getPort(ID(\\A))))
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for (auto bit : sigmap(cell->getPort(ID(A))))
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sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
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j = 0;
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for (auto bit : sigmap(cell->getPort(ID(\\B))))
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for (auto bit : sigmap(cell->getPort(ID(B))))
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sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
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}
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}
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@ -128,9 +128,9 @@ struct ShregmapTechXilinx7 : ShregmapTech
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if (it == sigbit_to_shiftx_offset.end())
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return;
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if (cell) {
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if (cell->type == ID($shiftx) && port == ID(\\A))
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if (cell->type == ID($shiftx) && port == ID(A))
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return;
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if (cell->type == ID($mux) && port.in(ID(\\A), ID(\\B)))
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if (cell->type == ID($mux) && port.in(ID(A), ID(B)))
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return;
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}
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sigbit_to_shiftx_offset.erase(it);
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@ -178,17 +178,17 @@ struct ShregmapTechXilinx7 : ShregmapTech
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// Only map if $shiftx exclusively covers the shift register
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if (shiftx->type == ID($shiftx)) {
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if (GetSize(taps) > shiftx->getParam(ID(\\A_WIDTH)).as_int())
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if (GetSize(taps) > shiftx->getParam(ID(A_WIDTH)).as_int())
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return false;
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// Due to padding the most significant bits of A may be 1'bx,
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// and if so, discount them
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if (GetSize(taps) < shiftx->getParam(ID(\\A_WIDTH)).as_int()) {
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const SigSpec A = shiftx->getPort(ID(\\A));
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const int A_width = shiftx->getParam(ID(\\A_WIDTH)).as_int();
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if (GetSize(taps) < shiftx->getParam(ID(A_WIDTH)).as_int()) {
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const SigSpec A = shiftx->getPort(ID(A));
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const int A_width = shiftx->getParam(ID(A_WIDTH)).as_int();
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for (int i = GetSize(taps); i < A_width; ++i)
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if (A[i] != RTLIL::Sx) return false;
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}
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else if (GetSize(taps) != shiftx->getParam(ID(\\A_WIDTH)).as_int())
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else if (GetSize(taps) != shiftx->getParam(ID(A_WIDTH)).as_int())
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return false;
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}
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else if (shiftx->type == ID($mux)) {
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@ -210,32 +210,32 @@ struct ShregmapTechXilinx7 : ShregmapTech
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auto newcell = cell->module->addCell(NEW_ID, ID($__XILINX_SHREG_));
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newcell->set_src_attribute(cell->get_src_attribute());
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newcell->setParam(ID(\\DEPTH), cell->getParam(ID(\\DEPTH)));
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newcell->setParam(ID(\\INIT), cell->getParam(ID(\\INIT)));
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newcell->setParam(ID(\\CLKPOL), cell->getParam(ID(\\CLKPOL)));
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newcell->setParam(ID(\\ENPOL), cell->getParam(ID(\\ENPOL)));
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newcell->setParam(ID(DEPTH), cell->getParam(ID(DEPTH)));
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newcell->setParam(ID(INIT), cell->getParam(ID(INIT)));
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newcell->setParam(ID(CLKPOL), cell->getParam(ID(CLKPOL)));
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newcell->setParam(ID(ENPOL), cell->getParam(ID(ENPOL)));
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newcell->setPort(ID(\\C), cell->getPort(ID(\\C)));
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newcell->setPort(ID(\\D), cell->getPort(ID(\\D)));
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if (cell->hasPort(ID(\\E)))
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newcell->setPort(ID(\\E), cell->getPort(ID(\\E)));
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newcell->setPort(ID(C), cell->getPort(ID(C)));
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newcell->setPort(ID(D), cell->getPort(ID(D)));
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if (cell->hasPort(ID(E)))
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newcell->setPort(ID(E), cell->getPort(ID(E)));
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Cell* shiftx = std::get<0>(it->second);
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RTLIL::SigSpec l_wire, q_wire;
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if (shiftx->type == ID($shiftx)) {
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l_wire = shiftx->getPort(ID(\\B));
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q_wire = shiftx->getPort(ID(\\Y));
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shiftx->setPort(ID(\\Y), cell->module->addWire(NEW_ID));
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l_wire = shiftx->getPort(ID(B));
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q_wire = shiftx->getPort(ID(Y));
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shiftx->setPort(ID(Y), cell->module->addWire(NEW_ID));
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}
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else if (shiftx->type == ID($mux)) {
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l_wire = shiftx->getPort(ID(\\S));
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q_wire = shiftx->getPort(ID(\\Y));
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shiftx->setPort(ID(\\Y), cell->module->addWire(NEW_ID));
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l_wire = shiftx->getPort(ID(S));
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q_wire = shiftx->getPort(ID(Y));
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shiftx->setPort(ID(Y), cell->module->addWire(NEW_ID));
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}
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else log_abort();
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newcell->setPort(ID(\\Q), q_wire);
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newcell->setPort(ID(\\L), l_wire);
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newcell->setPort(ID(Q), q_wire);
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newcell->setPort(ID(L), l_wire);
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return false;
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}
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@ -263,16 +263,16 @@ struct ShregmapWorker
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{
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for (auto wire : module->wires())
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{
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if (wire->port_output || wire->get_bool_attribute(ID(\\keep))) {
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if (wire->port_output || wire->get_bool_attribute(ID(keep))) {
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for (auto bit : sigmap(wire)) {
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sigbit_with_non_chain_users.insert(bit);
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if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
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}
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}
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if (wire->attributes.count(ID(\\init))) {
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if (wire->attributes.count(ID(init))) {
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SigSpec initsig = sigmap(wire);
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Const initval = wire->attributes.at(ID(\\init));
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Const initval = wire->attributes.at(ID(init));
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for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
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if (initval[i] == State::S0 && !opts.zinit)
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sigbit_init[initsig[i]] = false;
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@ -283,7 +283,7 @@ struct ShregmapWorker
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for (auto cell : module->cells())
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{
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if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(\\keep)))
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if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(keep)))
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{
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IdString d_port = opts.ffcells.at(cell->type).first;
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IdString q_port = opts.ffcells.at(cell->type).second;
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@ -474,7 +474,7 @@ struct ShregmapWorker
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initval.push_back(State::S0);
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remove_init.insert(bit);
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}
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first_cell->setParam(ID(\\INIT), initval);
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first_cell->setParam(ID(INIT), initval);
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}
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if (opts.zinit)
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@ -497,13 +497,13 @@ struct ShregmapWorker
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if (first_cell->type == ID($_DFFE_PP_)) param_clkpol = 1, param_enpol = 1;
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log_assert(param_clkpol >= 0);
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first_cell->setParam(ID(\\CLKPOL), param_clkpol);
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if (opts.ffe) first_cell->setParam(ID(\\ENPOL), param_enpol);
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first_cell->setParam(ID(CLKPOL), param_clkpol);
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if (opts.ffe) first_cell->setParam(ID(ENPOL), param_enpol);
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}
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first_cell->type = shreg_cell_type_str;
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first_cell->setPort(q_port, last_cell->getPort(q_port));
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first_cell->setParam(ID(\\DEPTH), depth);
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first_cell->setParam(ID(DEPTH), depth);
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if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
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remove_cells.insert(first_cell);
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@ -521,18 +521,18 @@ struct ShregmapWorker
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for (auto wire : module->wires())
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{
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if (wire->attributes.count(ID(\\init)) == 0)
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if (wire->attributes.count(ID(init)) == 0)
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continue;
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SigSpec initsig = sigmap(wire);
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Const &initval = wire->attributes.at(ID(\\init));
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Const &initval = wire->attributes.at(ID(init));
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for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
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if (remove_init.count(initsig[i]))
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initval[i] = State::Sx;
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if (SigSpec(initval).is_fully_undef())
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wire->attributes.erase(ID(\\init));
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wire->attributes.erase(ID(init));
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}
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remove_cells.clear();
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@ -717,19 +717,19 @@ struct ShregmapPass : public Pass {
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bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
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if (clk_pos && en_none)
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opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q)));
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opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
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if (clk_neg && en_none)
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opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q)));
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opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
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if (clk_pos && en_pos)
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opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q)));
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opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
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if (clk_pos && en_neg)
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opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q)));
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opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
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if (clk_neg && en_pos)
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opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q)));
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opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
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if (clk_neg && en_neg)
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opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID(\\D)), IdString(ID(\\Q)));
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opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
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if (en_pos || en_neg)
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opts.ffe = true;
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