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ID(\\.*) -> ID(.*)

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This commit is contained in:
Eddie Hung 2019-08-15 10:25:54 -07:00
parent 467c34eff0
commit 02dead2e60
25 changed files with 766 additions and 766 deletions
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96
passes/techmap/muxcover.cc
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@ -116,13 +116,13 @@ struct MuxcoverWorker
if (!cell->input(conn.first))
continue;
for (auto bit : sigmap(conn.second)) {
if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID(\\S))
if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID(S))
roots.insert(bit);
used_once.insert(bit);
}
}
if (cell->type == ID($_MUX_))
sig_to_mux[sigmap(cell->getPort(ID(\\Y)))] = cell;
sig_to_mux[sigmap(cell->getPort(ID(Y)))] = cell;
}
log(" Treeifying %d MUXes:\n", GetSize(sig_to_mux));
@ -141,8 +141,8 @@ struct MuxcoverWorker
if (sig_to_mux.count(bit) && (bit == rootsig || !roots.count(bit))) {
Cell *c = sig_to_mux.at(bit);
tree.muxes[bit] = c;
wavefront.insert(sigmap(c->getPort(ID(\\A))));
wavefront.insert(sigmap(c->getPort(ID(\\B))));
wavefront.insert(sigmap(c->getPort(ID(A))));
wavefront.insert(sigmap(c->getPort(ID(B))));
}
}
@ -517,68 +517,68 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 2) {
count_muxes_by_type[0]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
cell->setPort(ID(\\A), mux.inputs[0]);
cell->setPort(ID(\\B), mux.inputs[1]);
cell->setPort(ID(\\S), mux.selects[0]);
cell->setPort(ID(\\Y), bit);
cell->setPort(ID(A), mux.inputs[0]);
cell->setPort(ID(B), mux.inputs[1]);
cell->setPort(ID(S), mux.selects[0]);
cell->setPort(ID(Y), bit);
return;
}
if (GetSize(mux.inputs) == 4) {
count_muxes_by_type[1]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
cell->setPort(ID(\\A), mux.inputs[0]);
cell->setPort(ID(\\B), mux.inputs[1]);
cell->setPort(ID(\\C), mux.inputs[2]);
cell->setPort(ID(\\D), mux.inputs[3]);
cell->setPort(ID(\\S), mux.selects[0]);
cell->setPort(ID(\\T), mux.selects[1]);
cell->setPort(ID(\\Y), bit);
cell->setPort(ID(A), mux.inputs[0]);
cell->setPort(ID(B), mux.inputs[1]);
cell->setPort(ID(C), mux.inputs[2]);
cell->setPort(ID(D), mux.inputs[3]);
cell->setPort(ID(S), mux.selects[0]);
cell->setPort(ID(T), mux.selects[1]);
cell->setPort(ID(Y), bit);
return;
}
if (GetSize(mux.inputs) == 8) {
count_muxes_by_type[2]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
cell->setPort(ID(\\A), mux.inputs[0]);
cell->setPort(ID(\\B), mux.inputs[1]);
cell->setPort(ID(\\C), mux.inputs[2]);
cell->setPort(ID(\\D), mux.inputs[3]);
cell->setPort(ID(\\E), mux.inputs[4]);
cell->setPort(ID(\\F), mux.inputs[5]);
cell->setPort(ID(\\G), mux.inputs[6]);
cell->setPort(ID(\\H), mux.inputs[7]);
cell->setPort(ID(\\S), mux.selects[0]);
cell->setPort(ID(\\T), mux.selects[1]);
cell->setPort(ID(\\U), mux.selects[2]);
cell->setPort(ID(\\Y), bit);
cell->setPort(ID(A), mux.inputs[0]);
cell->setPort(ID(B), mux.inputs[1]);
cell->setPort(ID(C), mux.inputs[2]);
cell->setPort(ID(D), mux.inputs[3]);
cell->setPort(ID(E), mux.inputs[4]);
cell->setPort(ID(F), mux.inputs[5]);
cell->setPort(ID(G), mux.inputs[6]);
cell->setPort(ID(H), mux.inputs[7]);
cell->setPort(ID(S), mux.selects[0]);
cell->setPort(ID(T), mux.selects[1]);
cell->setPort(ID(U), mux.selects[2]);
cell->setPort(ID(Y), bit);
return;
}
if (GetSize(mux.inputs) == 16) {
count_muxes_by_type[3]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
cell->setPort(ID(\\A), mux.inputs[0]);
cell->setPort(ID(\\B), mux.inputs[1]);
cell->setPort(ID(\\C), mux.inputs[2]);
cell->setPort(ID(\\D), mux.inputs[3]);
cell->setPort(ID(\\E), mux.inputs[4]);
cell->setPort(ID(\\F), mux.inputs[5]);
cell->setPort(ID(\\G), mux.inputs[6]);
cell->setPort(ID(\\H), mux.inputs[7]);
cell->setPort(ID(\\I), mux.inputs[8]);
cell->setPort(ID(\\J), mux.inputs[9]);
cell->setPort(ID(\\K), mux.inputs[10]);
cell->setPort(ID(\\L), mux.inputs[11]);
cell->setPort(ID(\\M), mux.inputs[12]);
cell->setPort(ID(\\N), mux.inputs[13]);
cell->setPort(ID(\\O), mux.inputs[14]);
cell->setPort(ID(\\P), mux.inputs[15]);
cell->setPort(ID(\\S), mux.selects[0]);
cell->setPort(ID(\\T), mux.selects[1]);
cell->setPort(ID(\\U), mux.selects[2]);
cell->setPort(ID(\\V), mux.selects[3]);
cell->setPort(ID(\\Y), bit);
cell->setPort(ID(A), mux.inputs[0]);
cell->setPort(ID(B), mux.inputs[1]);
cell->setPort(ID(C), mux.inputs[2]);
cell->setPort(ID(D), mux.inputs[3]);
cell->setPort(ID(E), mux.inputs[4]);
cell->setPort(ID(F), mux.inputs[5]);
cell->setPort(ID(G), mux.inputs[6]);
cell->setPort(ID(H), mux.inputs[7]);
cell->setPort(ID(I), mux.inputs[8]);
cell->setPort(ID(J), mux.inputs[9]);
cell->setPort(ID(K), mux.inputs[10]);
cell->setPort(ID(L), mux.inputs[11]);
cell->setPort(ID(M), mux.inputs[12]);
cell->setPort(ID(N), mux.inputs[13]);
cell->setPort(ID(O), mux.inputs[14]);
cell->setPort(ID(P), mux.inputs[15]);
cell->setPort(ID(S), mux.selects[0]);
cell->setPort(ID(T), mux.selects[1]);
cell->setPort(ID(U), mux.selects[2]);
cell->setPort(ID(V), mux.selects[3]);
cell->setPort(ID(Y), bit);
return;
}