3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00

ID(\\.*) -> ID(.*)

This commit is contained in:
Eddie Hung 2019-08-15 10:25:54 -07:00
parent 467c34eff0
commit 02dead2e60
25 changed files with 766 additions and 766 deletions

View file

@ -485,7 +485,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
cell_list.push_back(it.second);
if (it.second->type == ID($_NOT_))
notmap[sigmap(it.second->getPort(ID(\\A)))].insert(it.second);
notmap[sigmap(it.second->getPort(ID(A)))].insert(it.second);
}
std::map<std::string, int> stats;
@ -519,8 +519,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
sig = module->addWire(NEW_ID, GetSize(old_sig));
if (has_q && has_qn) {
for (auto &it : notmap[sigmap(old_sig)]) {
module->connect(it->getPort(ID(\\Y)), sig);
it->setPort(ID(\\Y), module->addWire(NEW_ID, GetSize(old_sig)));
module->connect(it->getPort(ID(Y)), sig);
it->setPort(ID(Y), module->addWire(NEW_ID, GetSize(old_sig)));
}
} else {
module->addNotGate(NEW_ID, sig, old_sig);