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ID(\\.*) -> ID(.*)

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This commit is contained in:
Eddie Hung 2019-08-15 10:25:54 -07:00
parent 467c34eff0
commit 02dead2e60
25 changed files with 766 additions and 766 deletions
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60
passes/techmap/abc9.cc
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@ -87,7 +87,7 @@ void handle_loops(RTLIL::Design *design)
// wires
pool<RTLIL::Const> ids_seen;
for (auto cell : module->cells()) {
auto it = cell->attributes.find(ID(\\abc_scc_id));
auto it = cell->attributes.find(ID(abc_scc_id));
if (it != cell->attributes.end()) {
auto r = ids_seen.insert(it->second);
if (r.second) {
@ -107,7 +107,7 @@ void handle_loops(RTLIL::Design *design)
log_assert(w->port_input);
log_assert(b.offset < GetSize(w));
}
w->set_bool_attribute(ID(\\abc_scc_break));
w->set_bool_attribute(ID(abc_scc_break));
module->swap_names(b.wire, w);
c.second = RTLIL::SigBit(w, b.offset);
}
@ -121,7 +121,7 @@ void handle_loops(RTLIL::Design *design)
std::vector<IdString> ports;
RTLIL::Module* box_module = design->module(cell->type);
if (box_module) {
auto ports_csv = box_module->attributes.at(ID(\\abc_scc_break), RTLIL::Const::from_string("")).decode_string();
auto ports_csv = box_module->attributes.at(ID(abc_scc_break), RTLIL::Const::from_string("")).decode_string();
for (const auto &port_name : split_tokens(ports_csv, ",")) {
auto port_id = RTLIL::escape_id(port_name);
auto kt = cell->connections_.find(port_id);
@ -140,7 +140,7 @@ void handle_loops(RTLIL::Design *design)
Wire *w = b.wire;
if (!w) continue;
w->port_output = true;
w->set_bool_attribute(ID(\\abc_scc_break));
w->set_bool_attribute(ID(abc_scc_break));
w = module->wire(stringf("%s.abci", w->name.c_str()));
if (!w) {
w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
@ -460,7 +460,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// the expose operation -- remove them from PO/PI
// and re-connecting them back together
for (auto wire : module->wires()) {
auto it = wire->attributes.find(ID(\\abc_scc_break));
auto it = wire->attributes.find(ID(abc_scc_break));
if (it != wire->attributes.end()) {
wire->attributes.erase(it);
log_assert(wire->port_output);
@ -535,7 +535,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
for (auto &it : mapped_mod->wires_) {
RTLIL::Wire *w = it.second;
RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
if (markgroups) remap_wire->attributes[ID(\\abcgroup)] = map_autoidx;
if (markgroups) remap_wire->attributes[ID(abcgroup)] = map_autoidx;
if (w->port_output) {
RTLIL::Wire *wire = module->wire(w->name);
log_assert(wire);
@ -564,7 +564,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
auto jt = abc_box.find(cell->type);
if (jt == abc_box.end()) {
RTLIL::Module* box_module = design->module(cell->type);
jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(\\abc_box_id)))).first;
jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc_box_id)))).first;
}
if (jt->second)
boxes.emplace_back(cell);
@ -582,13 +582,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Cell *cell = nullptr;
if (c->type == ID($_NOT_)) {
RTLIL::SigBit a_bit = c->getPort(ID(\\A));
RTLIL::SigBit y_bit = c->getPort(ID(\\Y));
RTLIL::SigBit a_bit = c->getPort(ID(A));
RTLIL::SigBit y_bit = c->getPort(ID(Y));
bit_users[a_bit].insert(c->name);
bit_drivers[y_bit].insert(c->name);
if (!a_bit.wire) {
c->setPort(ID(\\Y), module->addWire(NEW_ID));
c->setPort(ID(Y), module->addWire(NEW_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@ -616,7 +616,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
bit2sinks[cell->getPort(ID(\\A))].push_back(cell);
bit2sinks[cell->getPort(ID(A))].push_back(cell);
cell_stats[ID($lut)]++;
}
else
@ -625,18 +625,18 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
else
log_abort();
if (cell && markgroups) cell->attributes[ID(\\abcgroup)] = map_autoidx;
if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
continue;
}
cell_stats[RTLIL::unescape_id(c->type)]++;
RTLIL::Cell *existing_cell = nullptr;
if (c->type == ID($lut)) {
if (GetSize(c->getPort(ID(\\A))) == 1 && c->getParam(ID(\\LUT)) == RTLIL::Const::from_string("01")) {
SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID(\\A)).as_wire()->name));
SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID(\\Y)).as_wire()->name));
if (GetSize(c->getPort(ID(A))) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID(A)).as_wire()->name));
SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID(Y)).as_wire()->name));
module->connect(my_y, my_a);
if (markgroups) c->attributes[ID(\\abcgroup)] = map_autoidx;
if (markgroups) c->attributes[ID(abcgroup)] = map_autoidx;
log_abort();
continue;
}
@ -649,7 +649,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
module->swap_names(cell, existing_cell);
}
if (markgroups) cell->attributes[ID(\\abcgroup)] = map_autoidx;
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (existing_cell) {
cell->parameters = existing_cell->parameters;
cell->attributes = existing_cell->attributes;
@ -751,8 +751,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
if (it == not2drivers.end())
continue;
RTLIL::Cell *driver_lut = it->second;
RTLIL::SigBit a_bit = not_cell->getPort(ID(\\A));
RTLIL::SigBit y_bit = not_cell->getPort(ID(\\Y));
RTLIL::SigBit a_bit = not_cell->getPort(ID(A));
RTLIL::SigBit y_bit = not_cell->getPort(ID(Y));
RTLIL::Const driver_mask;
a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
@ -768,8 +768,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// Push downstream LUTs past inverter
for (auto sink_cell : jt->second) {
SigSpec A = sink_cell->getPort(ID(\\A));
RTLIL::Const mask = sink_cell->getParam(ID(\\LUT));
SigSpec A = sink_cell->getPort(ID(A));
RTLIL::Const mask = sink_cell->getParam(ID(LUT));
int index = 0;
for (; index < GetSize(A); index++)
if (A[index] == a_bit)
@ -782,8 +782,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
i += 1 << (index+1);
}
A[index] = y_bit;
sink_cell->setPort(ID(\\A), A);
sink_cell->setParam(ID(\\LUT), mask);
sink_cell->setPort(ID(A), A);
sink_cell->setParam(ID(LUT), mask);
}
// Since we have rewritten all sinks (which we know
@ -792,16 +792,16 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// that the original driving LUT will become dangling
// and get cleaned away
clone_lut:
driver_mask = driver_lut->getParam(ID(\\LUT));
driver_mask = driver_lut->getParam(ID(LUT));
for (auto &b : driver_mask.bits) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}
auto cell = module->addLut(NEW_ID,
driver_lut->getPort(ID(\\A)),
driver_lut->getPort(ID(A)),
y_bit,
driver_mask);
for (auto &bit : cell->connections_.at(ID(\\A))) {
for (auto &bit : cell->connections_.at(ID(A))) {
bit.wire = module->wires_.at(remap_name(bit.wire->name));
bit2sinks[bit].push_back(cell);
}
@ -1082,7 +1082,7 @@ struct Abc9Pass : public Pass {
dict<int,IdString> box_lookup;
for (auto m : design->modules()) {
auto it = m->attributes.find(ID(\\abc_box_id));
auto it = m->attributes.find(ID(abc_box_id));
if (it == m->attributes.end())
continue;
if (m->name.begins_with("$paramod"))
@ -1097,7 +1097,7 @@ struct Abc9Pass : public Pass {
for (auto mod : design->selected_modules())
{
if (mod->attributes.count(ID(\\abc_box_id)))
if (mod->attributes.count(ID(abc_box_id)))
continue;
if (mod->processes.size() > 0) {
@ -1153,14 +1153,14 @@ struct Abc9Pass : public Pass {
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
{
key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(\\C))), true, RTLIL::SigSpec());
key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
}
else
if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
{
bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(\\C))), this_en_pol, assign_map(cell->getPort(ID(\\E))));
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, assign_map(cell->getPort(ID(E))));
}
else
continue;