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Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff

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Claire Xenia Wolf 2022-12-21 14:50:23 +01:00
parent 1bc832a8e1 4a0ed35aab
commit 029b0aac7f
1 changed files with 10 additions and 14 deletions
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24
passes/cmds/xprop.cc
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@ -967,7 +967,7 @@ struct XpropWorker
if (!options.split_inputs && !options.split_outputs) if (!options.split_inputs && !options.split_outputs)
return; return;
vector<IdString> new_ports; int port_id = 1;
for (auto port : module->ports) { for (auto port : module->ports) {
auto wire = module->wire(port); auto wire = module->wire(port);
@ -983,16 +983,21 @@ struct XpropWorker
wire_d->port_input = wire->port_input; wire_d->port_input = wire->port_input;
wire_d->port_output = wire->port_output; wire_d->port_output = wire->port_output;
wire_d->port_id = GetSize(new_ports) + 1; wire_d->port_id = port_id++;
wire_x->port_input = wire->port_input; wire_x->port_input = wire->port_input;
wire_x->port_output = wire->port_output; wire_x->port_output = wire->port_output;
wire_x->port_id = GetSize(new_ports) + 2; wire_x->port_id = port_id++;
if (wire->port_output) { if (wire->port_output) {
auto enc = encoded(wire); auto enc = encoded(wire);
module->connect(wire_d, enc.is_1); module->connect(wire_d, enc.is_1);
module->connect(wire_x, enc.is_x); module->connect(wire_x, enc.is_x);
if (options.split_public) {
// Need to hide the original wire so split_public doesn't try to split it again
module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
}
} else { } else {
auto enc = encoded(wire, true); auto enc = encoded(wire, true);
@ -1004,18 +1009,12 @@ struct XpropWorker
wire->port_input = wire->port_output = false; wire->port_input = wire->port_output = false;
wire->port_id = 0; wire->port_id = 0;
new_ports.push_back(port_d);
new_ports.push_back(port_x);
continue; continue;
} }
} }
wire->port_id = GetSize(new_ports) + 1; wire->port_id = port_id++;
new_ports.push_back(port);
} }
module->ports = new_ports;
module->fixup_ports(); module->fixup_ports();
} }
@ -1037,10 +1036,7 @@ struct XpropWorker
module->connect(wire_d, enc.is_1); module->connect(wire_d, enc.is_1);
module->connect(wire_x, enc.is_x); module->connect(wire_x, enc.is_x);
module->wires_.erase(wire->name); module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
wire->attributes.erase(ID::fsm_encoding);
wire->name = NEW_ID_SUFFIX(wire->name.c_str());
module->wires_[wire->name] = wire;
} }
} }