mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-03 04:41:22 +00:00
Remove clkpart
This commit is contained in:
Eddie Hung
parent
864bff14f1
commit
02786b0aa0
3 changed files with 0 additions and 313 deletions
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@ -2,5 +2,4 @@
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OBJS += passes/hierarchy/hierarchy.o
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OBJS += passes/hierarchy/hierarchy.o
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OBJS += passes/hierarchy/uniquify.o
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OBJS += passes/hierarchy/uniquify.o
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OBJS += passes/hierarchy/submod.o
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OBJS += passes/hierarchy/submod.o
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OBJS += passes/hierarchy/clkpart.o
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@ -1,308 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ClkPartPass : public Pass {
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ClkPartPass() : Pass("clkpart", "partition design according to clock/enable domain") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" clkpart [options] [selection]\n");
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log("\n");
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log("Partition the contents of selected modules according to the clock (and optionally\n");
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log("the enable) domains of its $_DFF* cells by extracting them into sub-modules,\n");
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log("using the `submod` command.\n");
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log("\n");
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log(" -set_attr <name> <value>\n");
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log(" set the specified attribute on all sub-modules created.\n");
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log("\n");
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log(" -unpart <name>\n");
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log(" undo this operation within the selected modules, by flattening those\n");
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log(" attached with an <name> attribute into those modules without this\n");
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log(" attribute.\n");
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log("\n");
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log(" -enable\n");
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log(" also consider enable domains.\n");
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log("\n");
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}
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bool unpart_mode, enable_mode;
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IdString attr_name;
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Const attr_value;
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void clear_flags() YS_OVERRIDE
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{
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unpart_mode = false;
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enable_mode = false;
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attr_name = IdString();
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attr_value = Const();
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing CLKPART pass (partition design according to clock/enable domain).\n");
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log_push();
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-set_attr" && argidx+2 < args.size()) {
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attr_name = RTLIL::escape_id(args[++argidx]);
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attr_value = args[argidx++];
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continue;
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}
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if (args[argidx] == "-unpart" && argidx+1 < args.size()) {
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unpart_mode = true;
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attr_name = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-enable") {
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enable_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (unpart_mode)
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unpart(design);
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else
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part(design);
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log_pop();
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}
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void part(RTLIL::Design *design)
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{
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CellTypes ct(design);
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SigMap assign_map;
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std::vector<std::string> new_submods;
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log_header(design, "Summary of detected clock domains:\n");
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for (auto mod : design->selected_modules())
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{
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if (mod->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(mod));
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continue;
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}
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assign_map.set(mod);
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std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
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pool<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
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pool<RTLIL::Cell*> expand_queue, next_expand_queue;
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pool<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
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pool<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
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typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
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std::map<clkdomain_t, vector<Cell*>> assigned_cells;
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std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
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std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
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std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
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for (auto cell : all_cells)
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{
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clkdomain_t key;
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for (auto &conn : cell->connections())
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for (auto bit : conn.second) {
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bit = assign_map(bit);
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if (bit.wire != nullptr) {
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cell_to_bit[cell].insert(bit);
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bit_to_cell[bit].insert(cell);
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if (ct.cell_input(cell->type, conn.first)) {
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cell_to_bit_up[cell].insert(bit);
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bit_to_cell_down[bit].insert(cell);
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}
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if (ct.cell_output(cell->type, conn.first)) {
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cell_to_bit_down[cell].insert(bit);
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bit_to_cell_up[bit].insert(cell);
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}
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}
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}
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if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
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{
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key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
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}
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else
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if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
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{
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bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
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bool this_en_pol = !enable_mode || cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
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key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec());
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}
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else
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if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
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ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
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{
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bool this_clk_pol = cell->type.in(ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_));
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log_assert(!enable_mode); // TODO
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key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
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}
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else
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continue;
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unassigned_cells.erase(cell);
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expand_queue.insert(cell);
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expand_queue_up.insert(cell);
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expand_queue_down.insert(cell);
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assigned_cells[key].push_back(cell);
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assigned_cells_reverse[cell] = key;
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}
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while (!expand_queue_up.empty() || !expand_queue_down.empty())
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{
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if (!expand_queue_up.empty())
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{
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RTLIL::Cell *cell = *expand_queue_up.begin();
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clkdomain_t key = assigned_cells_reverse.at(cell);
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expand_queue_up.erase(cell);
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for (auto bit : cell_to_bit_up[cell])
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for (auto c : bit_to_cell_up[bit])
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if (unassigned_cells.count(c)) {
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unassigned_cells.erase(c);
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next_expand_queue_up.insert(c);
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assigned_cells[key].push_back(c);
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assigned_cells_reverse[c] = key;
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expand_queue.insert(c);
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}
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}
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if (!expand_queue_down.empty())
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{
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RTLIL::Cell *cell = *expand_queue_down.begin();
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clkdomain_t key = assigned_cells_reverse.at(cell);
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expand_queue_down.erase(cell);
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for (auto bit : cell_to_bit_down[cell])
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for (auto c : bit_to_cell_down[bit])
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if (unassigned_cells.count(c)) {
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unassigned_cells.erase(c);
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next_expand_queue_up.insert(c);
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assigned_cells[key].push_back(c);
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assigned_cells_reverse[c] = key;
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expand_queue.insert(c);
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}
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}
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if (expand_queue_up.empty() && expand_queue_down.empty()) {
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expand_queue_up.swap(next_expand_queue_up);
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expand_queue_down.swap(next_expand_queue_down);
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}
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}
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while (!expand_queue.empty())
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{
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RTLIL::Cell *cell = *expand_queue.begin();
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clkdomain_t key = assigned_cells_reverse.at(cell);
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expand_queue.erase(cell);
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for (auto bit : cell_to_bit.at(cell)) {
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for (auto c : bit_to_cell[bit])
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if (unassigned_cells.count(c)) {
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unassigned_cells.erase(c);
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next_expand_queue.insert(c);
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assigned_cells[key].push_back(c);
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assigned_cells_reverse[c] = key;
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}
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bit_to_cell[bit].clear();
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}
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if (expand_queue.empty())
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expand_queue.swap(next_expand_queue);
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}
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clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
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for (auto cell : unassigned_cells) {
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assigned_cells[key].push_back(cell);
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assigned_cells_reverse[cell] = key;
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}
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clkdomain_t largest_domain;
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int largest_domain_size = 0;
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log(" module %s\n", mod->name.c_str());
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for (auto &it : assigned_cells) {
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log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
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std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
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std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
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if (GetSize(it.second) > largest_domain_size) {
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largest_domain = it.first;
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largest_domain_size = GetSize(it.second);
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}
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}
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for (auto &it : assigned_cells) {
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if (it.first == largest_domain)
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continue;
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auto clk = std::get<1>(it.first);
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auto en = std::get<3>(it.first);
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std::string submod = stringf("clk=%s%s%s%s%s",
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std::get<0>(it.first) ? "" : "!", clk.empty() ? "" : log_signal(clk),
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std::get<2>(it.first) ? "" : "!", en.empty() ? "" : ".en=", en.empty() ? "" : log_signal(en));
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for (auto c : it.second)
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c->attributes[ID(submod)] = submod;
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new_submods.push_back(stringf("%s_%s", mod->name.c_str(), submod.c_str()));
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}
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}
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Pass::call(design, "submod -hidden");
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if (!attr_name.empty())
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for (auto m : new_submods)
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design->module(m)->attributes[attr_name] = attr_value;
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}
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void unpart(RTLIL::Design *design)
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{
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vector<Module*> keeped;
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for (auto mod : design->selected_modules()) {
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if (mod->get_bool_attribute(attr_name))
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continue;
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if (mod->get_bool_attribute(ID(keep_hierarchy)))
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continue;
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keeped.push_back(mod);
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mod->set_bool_attribute(ID(keep_hierarchy));
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}
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Pass::call(design, "flatten");
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for (auto mod : keeped)
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mod->set_bool_attribute(ID(keep_hierarchy), false);
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}
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} ClkPartPass;
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PRIVATE_NAMESPACE_END
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@ -513,7 +513,6 @@ struct SynthXilinxPass : public ScriptPass
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if (check_label("map_ffs")) {
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if (check_label("map_ffs")) {
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if (abc9 || help_mode) {
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if (abc9 || help_mode) {
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run("clkpart -set_attr clkpart 1", "('-abc9' only)");
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run("techmap -map " + ff_map_file, "('-abc9' only)");
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run("techmap -map " + ff_map_file, "('-abc9' only)");
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}
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}
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}
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}
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@ -561,9 +560,6 @@ struct SynthXilinxPass : public ScriptPass
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}
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}
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if (check_label("finalize")) {
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if (check_label("finalize")) {
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if (help_mode || abc9)
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run("clkpart -unpart clkpart", "(only if 'abc9')");
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bool do_iopad = iopad || (ise && !noiopad);
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bool do_iopad = iopad || (ise && !noiopad);
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if (help_mode || !noclkbuf) {
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if (help_mode || !noclkbuf) {
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if (help_mode || do_iopad)
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if (help_mode || do_iopad)
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