diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 28cbb4f4d..52871b881 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -188,6 +188,11 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
 
 void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool escape_comment = false)
 {
+	if (data.flags & RTLIL::CONST_FLAG_ID) {
+		f << stringf("%s", data.decode_string().c_str());
+		return;
+	}
+
 	bool set_signed = (data.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
 	if (width < 0)
 		width = data.bits.size() - offset;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 7a0b6b9c7..d34e63973 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -50,7 +50,8 @@ namespace RTLIL
 		CONST_FLAG_NONE   = 0,
 		CONST_FLAG_STRING = 1,
 		CONST_FLAG_SIGNED = 2,  // only used for parameters
-		CONST_FLAG_REAL   = 4   // only used for parameters
+		CONST_FLAG_REAL   = 4,  // only used for parameters
+		CONST_FLAG_ID     = 5
 	};
 
 	struct Const;