3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-10 08:03:26 +00:00

hashlib: fixes from jix

This commit is contained in:
Emil J. Tywoniak 2024-11-20 17:06:49 +01:00
parent ed70038aa1
commit 026e9dae9d
4 changed files with 15 additions and 15 deletions

View file

@ -60,8 +60,6 @@ struct ModIndex : public RTLIL::Monitor
{
bool is_input, is_output;
pool<PortInfo> ports;
// SigBitInfo() : SigBitInfo{} {}
// SigBitInfo& operator=(const SigBitInfo&) = default;
SigBitInfo() : is_input(false), is_output(false) { }
@ -310,7 +308,6 @@ struct ModWalker
RTLIL::IdString port;
int offset;
PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}
// PortBit& operator=(const PortBit&) = default;
bool operator<(const PortBit &other) const {
if (cell != other.cell)