diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index f34faf37c..c9fe98a74 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -54,6 +54,7 @@ OBJS += passes/techmap/flowmap.o
 OBJS += passes/techmap/extractinv.o
 OBJS += passes/techmap/cellmatch.o
 OBJS += passes/techmap/clockgate.o
+OBJS += passes/techmap/constmap.o
 endif
 
 ifeq ($(DISABLE_SPAWN),0)
diff --git a/passes/techmap/constmap.cc b/passes/techmap/constmap.cc
new file mode 100644
index 000000000..f0757403d
--- /dev/null
+++ b/passes/techmap/constmap.cc
@@ -0,0 +1,106 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2025  King Lok Chung <king.chung@manchester.ac.uk>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static std::string celltype, cell_portname, cell_paramname;
+
+static RTLIL::Module *module;
+static RTLIL::SigChunk value;
+
+void constmap_worker(RTLIL::SigSpec &sig)
+{
+	if (sig.is_fully_const()){
+		value = module->addWire(NEW_ID, sig.size());
+		RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
+		cell->setParam(cell_paramname, sig.as_const());
+		cell->setPort(cell_portname, value);
+		sig = value;
+	}
+}
+
+struct ConstmapPass : public Pass {
+	ConstmapPass() : Pass("constmap", "technology mapping of coarse constant value") { }
+	void help() override
+	{
+		log("\n");
+		log("    constmap [options] [selection]\n");
+		log("\n");
+		log("Map constants to a driver cell.\n");
+		log("\n");
+		log("    -cell <celltype> <portname> <paramname>\n");
+		log("        Replace constant bits with this cell.\n");
+		log("        The value of the constant will be stored to the parameter specified.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing CONSTMAP pass (mapping to constant driver).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-cell" && argidx+3 < args.size()){
+				celltype = RTLIL::escape_id(args[++argidx]);
+				cell_portname = RTLIL::escape_id(args[++argidx]);
+				cell_paramname = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+
+		if (design->has(celltype)) {
+			Module *existing = design->module(celltype);
+			bool has_port = false;
+			for (auto &p : existing->ports){
+				if (p == cell_portname){
+					has_port = true;
+					break;
+				}
+			}
+			if (!has_port)
+				log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype.c_str(), cell_portname.c_str());
+
+			bool has_param = false;
+			for (auto &p : existing->avail_parameters){
+				if (p == cell_paramname)
+					has_param = true;
+			}
+
+			if (!has_param)
+				log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype.c_str(), cell_paramname.c_str());
+		}
+
+
+		for (auto mod : design->selected_modules())
+		{
+			module = mod;
+			module->rewrite_sigspecs(constmap_worker);
+		}
+	}
+} ConstmapPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/tests/techmap/constmap.ys b/tests/techmap/constmap.ys
new file mode 100644
index 000000000..6945cf514
--- /dev/null
+++ b/tests/techmap/constmap.ys
@@ -0,0 +1,43 @@
+read_verilog << EOT
+
+module test();
+  wire [31:0] in;
+  wire [31:0] out;
+  assign out = in + 16;
+endmodule
+
+EOT
+
+constmap -cell const_cell O value
+select -assert-count 1 t:const_cell r:value=16 %i
+
+design -reset
+
+read_verilog -lib << EOT
+module const_cell(O);
+parameter value=0;
+output O;
+endmodule
+EOT
+
+read_verilog << EOT
+
+module test();
+  wire [31:0] in;
+  wire [31:0] out1;
+  wire [31:0] out2;
+  assign out1 = in + 16;
+  assign out2 = in + 32;
+endmodule
+
+EOT
+
+constmap -cell const_cell O value
+
+select -assert-count 2 t:const_cell
+select -assert-count 1 r:value=16
+select -assert-count 1 r:value=32
+select -assert-count 1 test/out1 %ci* r:value=16 %i
+select -assert-count 1 test/out2 %ci* r:value=32 %i
+select -assert-count 1 t:const_cell r:value=16 %i
+select -assert-count 1 t:const_cell r:value=32 %i