From 60bcb93e8bedf8f2144c02380fd20ea99b5d59ad Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 28 Aug 2025 18:10:00 +0200 Subject: [PATCH 01/14] write_rtlil: don't sort --- backends/rtlil/rtlil_backend.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index adde37356..2d38982f3 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -456,8 +456,6 @@ struct RTLILBackend : public Backend { } extra_args(f, filename, args, argidx); - design->sort(); - log("Output filename: %s\n", filename.c_str()); *f << stringf("# Generated by %s\n", yosys_maybe_version()); From 7ecf0747b363d10a86e2569f10e694c4692c98e4 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:21:30 +0200 Subject: [PATCH 02/14] hashlib: add insertion order const iterator --- kernel/hashlib.h | 18 ++++++++++++++---- kernel/utils.h | 11 +++++++++++ 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index 9c53e6687..3136494c7 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -558,13 +558,16 @@ public: int index; const_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { } public: - typedef std::forward_iterator_tag iterator_category; + typedef std::bidirectional_iterator_tag iterator_category; typedef std::pair value_type; typedef ptrdiff_t difference_type; - typedef std::pair* pointer; - typedef std::pair& reference; + typedef const std::pair* pointer; + typedef const std::pair& reference; const_iterator() { } const_iterator operator++() { index--; return *this; } + const_iterator operator++(int) { const_iterator tmp = *this; index--; return tmp; } + const_iterator operator--() { index++; return *this; } + const_iterator operator--(int) { const_iterator tmp = *this; index++; return tmp; } const_iterator operator+=(int amt) { index -= amt; return *this; } bool operator<(const const_iterator &other) const { return index > other.index; } bool operator==(const const_iterator &other) const { return index == other.index; } @@ -598,6 +601,13 @@ public: const std::pair *operator->() const { return &ptr->entries[index].udata; } operator const_iterator() const { return const_iterator(ptr, index); } }; + using reverse_iterator = std::reverse_iterator; + reverse_iterator rbegin() const { + return std::make_reverse_iterator(end()); + } + reverse_iterator rend() const { + return std::make_reverse_iterator(begin()); + } constexpr dict() { @@ -847,7 +857,7 @@ public: const_iterator begin() const { return const_iterator(this, int(entries.size())-1); } const_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); } - const_iterator end() const { return const_iterator(nullptr, -1); } + const_iterator end() const { return const_iterator(this, -1); } }; template diff --git a/kernel/utils.h b/kernel/utils.h index 6c9fe36a5..5c739aceb 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -21,6 +21,7 @@ // do not depend on any other components of yosys (except stuff like log_*). #include "kernel/yosys.h" +#include #ifndef UTILS_H #define UTILS_H @@ -276,6 +277,16 @@ inline int ceil_log2(int x) #endif } +template +auto reversed(const T& container) { + struct reverse_view { + const T& cont; + auto begin() const { return cont.rbegin(); } + auto end() const { return cont.rend(); } + }; + return reverse_view{container}; +} + YOSYS_NAMESPACE_END #endif From 17cb0f3fa64ac1f0ec204ba59cd79dde6c282a6b Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:21:42 +0200 Subject: [PATCH 03/14] raise_error: whitespace --- passes/tests/raise_error.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/tests/raise_error.cc b/passes/tests/raise_error.cc index 588a40806..d7b8b10d3 100644 --- a/passes/tests/raise_error.cc +++ b/passes/tests/raise_error.cc @@ -47,7 +47,7 @@ struct RaiseErrorPass : public Pass { extra_args(args, argidx, design, true); RTLIL::NamedObject *err_obj = nullptr; - + for (auto mod : design->all_selected_modules()) { if (mod->has_attribute(ID::raise_error)) { err_obj = mod->clone(); From 10643951a1fc5742e71df6e6cedc90b643b0a7d4 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:22:03 +0200 Subject: [PATCH 04/14] bugpoint: don't sort --- passes/cmds/bugpoint.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 08dc76dda..25c384fcc 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -122,8 +122,6 @@ struct BugpointPass : public Pass { int run_yosys(RTLIL::Design *design, string runner, string yosys_cmd, string yosys_arg, string suffix, bool catch_err) { - design->sort(); - string bugpoint_file = "bugpoint-case"; if (suffix.size()) bugpoint_file += stringf(".%.8s", suffix.c_str()); From 582c5a4f13abbb7cbf6230c627942594df7638cb Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:22:35 +0200 Subject: [PATCH 05/14] write_rtlil: dump in insertion order --- backends/rtlil/rtlil_backend.cc | 144 ++++++++++++++------------------ backends/rtlil/rtlil_backend.h | 1 + 2 files changed, 62 insertions(+), 83 deletions(-) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 2d38982f3..064bb7044 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -24,12 +24,23 @@ #include "rtlil_backend.h" #include "kernel/yosys.h" +#include "kernel/utils.h" #include +#include USING_YOSYS_NAMESPACE using namespace RTLIL_BACKEND; YOSYS_NAMESPACE_BEGIN +void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj) +{ + for (const auto& [name, value] : reversed(obj->attributes)) { + f << stringf("%s" "attribute %s ", indent.c_str(), name.c_str()); + dump_const(f, value); + f << stringf("\n"); + } +} + void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint) { if (width < 0) @@ -110,8 +121,8 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo dump_sigchunk(f, sig.as_chunk(), autoint); } else { f << stringf("{ "); - for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) { - dump_sigchunk(f, *it, false); + for (const auto& chunk : reversed(sig.chunks())) { + dump_sigchunk(f, chunk, false); f << stringf(" "); } f << stringf("}"); @@ -120,11 +131,7 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire) { - for (auto &it : wire->attributes) { - f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); - dump_const(f, it.second); - f << stringf("\n"); - } + dump_attributes(f, indent, wire); if (wire->driverCell_) { f << stringf("%s" "# driver %s %s\n", indent.c_str(), wire->driverCell()->name.c_str(), wire->driverPort().c_str()); @@ -149,11 +156,7 @@ void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL:: void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory) { - for (auto &it : memory->attributes) { - f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); - dump_const(f, it.second); - f << stringf("\n"); - } + dump_attributes(f, indent, memory); f << stringf("%s" "memory ", indent.c_str()); if (memory->width != 1) f << stringf("width %d ", memory->width); @@ -166,23 +169,19 @@ void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell) { - for (auto &it : cell->attributes) { - f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); - dump_const(f, it.second); - f << stringf("\n"); - } + dump_attributes(f, indent, cell); f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str()); - for (auto &it : cell->parameters) { + for (const auto& [name, param] : reversed(cell->parameters)) { f << stringf("%s parameter%s%s %s ", indent.c_str(), - (it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", - (it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "", - it.first.c_str()); - dump_const(f, it.second); + (param.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", + (param.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "", + name.c_str()); + dump_const(f, param); f << stringf("\n"); } - for (auto &it : cell->connections()) { - f << stringf("%s connect %s ", indent.c_str(), it.first.c_str()); - dump_sigspec(f, it.second); + for (const auto& [port, sig] : reversed(cell->connections_)) { + f << stringf("%s connect %s ", indent.c_str(), port.c_str()); + dump_sigspec(f, sig); f << stringf("\n"); } f << stringf("%s" "end\n", indent.c_str()); @@ -190,47 +189,38 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL:: void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs) { - for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) - { + for (const auto& [lhs, rhs] : cs->actions) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, it->first); + dump_sigspec(f, lhs); f << stringf(" "); - dump_sigspec(f, it->second); + dump_sigspec(f, rhs); f << stringf("\n"); } - for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it) - dump_proc_switch(f, indent, *it); + for (const auto& sw : cs->switches) + dump_proc_switch(f, indent, sw); } void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw) { - for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str()); - dump_const(f, it->second); - f << stringf("\n"); - } + dump_attributes(f, indent, sw); f << stringf("%s" "switch ", indent.c_str()); dump_sigspec(f, sw->signal); f << stringf("\n"); - for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) + for (const auto case_ : sw->cases) { - for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) { - f << stringf("%s attribute %s ", indent.c_str(), ait->first.c_str()); - dump_const(f, ait->second); - f << stringf("\n"); - } + dump_attributes(f, indent, case_); f << stringf("%s case ", indent.c_str()); - for (size_t i = 0; i < (*it)->compare.size(); i++) { + for (size_t i = 0; i < case_->compare.size(); i++) { if (i > 0) f << stringf(" , "); - dump_sigspec(f, (*it)->compare[i]); + dump_sigspec(f, case_->compare[i]); } f << stringf("\n"); - dump_proc_case_body(f, indent + " ", *it); + dump_proc_case_body(f, indent + " ", case_); } f << stringf("%s" "end\n", indent.c_str()); @@ -253,20 +243,16 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT case RTLIL::STi: f << stringf("init\n"); break; } - for (auto &it: sy->actions) { + for (const auto& [lhs, rhs] : sy->actions) { f << stringf("%s update ", indent.c_str()); - dump_sigspec(f, it.first); + dump_sigspec(f, lhs); f << stringf(" "); - dump_sigspec(f, it.second); + dump_sigspec(f, rhs); f << stringf("\n"); } for (auto &it: sy->mem_write_actions) { - for (auto it2 = it.attributes.begin(); it2 != it.attributes.end(); ++it2) { - f << stringf("%s attribute %s ", indent.c_str(), it2->first.c_str()); - dump_const(f, it2->second); - f << stringf("\n"); - } + dump_attributes(f, indent, &it); f << stringf("%s memwr %s ", indent.c_str(), it.memid.c_str()); dump_sigspec(f, it.address); f << stringf(" "); @@ -281,15 +267,11 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc) { - for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str()); - dump_const(f, it->second); - f << stringf("\n"); - } + dump_attributes(f, indent, proc); f << stringf("%s" "process %s\n", indent.c_str(), proc->name.c_str()); dump_proc_case_body(f, indent + " ", &proc->root_case); - for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it) - dump_proc_sync(f, indent + " ", *it); + for (auto* sync : proc->syncs) + dump_proc_sync(f, indent + " ", sync); f << stringf("%s" "end\n", indent.c_str()); } @@ -309,11 +291,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (print_header) { - for (auto it = module->attributes.begin(); it != module->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str()); - dump_const(f, it->second); - f << stringf("\n"); - } + dump_attributes(f, indent, module); f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str()); @@ -335,40 +313,40 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (print_body) { - for (auto it : module->wires()) - if (!only_selected || design->selected(module, it)) { + for (const auto& [_, wire] : reversed(module->wires_)) + if (!only_selected || design->selected(module, wire)) { if (only_selected) f << stringf("\n"); - dump_wire(f, indent + " ", it); + dump_wire(f, indent + " ", wire); } - for (auto it : module->memories) - if (!only_selected || design->selected(module, it.second)) { + for (const auto& [_, mem] : reversed(module->memories)) + if (!only_selected || design->selected(module, mem)) { if (only_selected) f << stringf("\n"); - dump_memory(f, indent + " ", it.second); + dump_memory(f, indent + " ", mem); } - for (auto it : module->cells()) - if (!only_selected || design->selected(module, it)) { + for (const auto& [_, cell] : reversed(module->cells_)) + if (!only_selected || design->selected(module, cell)) { if (only_selected) f << stringf("\n"); - dump_cell(f, indent + " ", it); + dump_cell(f, indent + " ", cell); } - for (auto it : module->processes) - if (!only_selected || design->selected(module, it.second)) { + for (const auto& [_, process] : reversed(module->processes)) + if (!only_selected || design->selected(module, process)) { if (only_selected) f << stringf("\n"); - dump_proc(f, indent + " ", it.second); + dump_proc(f, indent + " ", process); } bool first_conn_line = true; - for (auto it = module->connections().begin(); it != module->connections().end(); ++it) { + for (const auto& [lhs, rhs] : module->connections()) { bool show_conn = !only_selected || design->selected_whole_module(module->name); if (!show_conn) { - RTLIL::SigSpec sigs = it->first; - sigs.append(it->second); + RTLIL::SigSpec sigs = lhs; + sigs.append(rhs); for (auto &c : sigs.chunks()) { if (c.wire == NULL || !design->selected(module, c.wire)) continue; @@ -378,7 +356,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (show_conn) { if (only_selected && first_conn_line) f << stringf("\n"); - dump_conn(f, indent + " ", it->first, it->second); + dump_conn(f, indent + " ", lhs, rhs); first_conn_line = false; } } @@ -394,7 +372,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl if (!flag_m) { int count_selected_mods = 0; - for (auto module : design->modules()) { + for (auto* module : design->modules()) { if (design->selected_whole_module(module->name)) flag_m = true; if (design->selected(module)) @@ -410,7 +388,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl f << stringf("autoidx %d\n", autoidx); } - for (auto module : design->modules()) { + for (const auto& [_, module] : reversed(design->modules_)) { if (!only_selected || design->selected(module)) { if (only_selected) f << stringf("\n"); diff --git a/backends/rtlil/rtlil_backend.h b/backends/rtlil/rtlil_backend.h index 35829729c..dd7347def 100644 --- a/backends/rtlil/rtlil_backend.h +++ b/backends/rtlil/rtlil_backend.h @@ -31,6 +31,7 @@ YOSYS_NAMESPACE_BEGIN namespace RTLIL_BACKEND { + void dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj); void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true); void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true); void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true); From 47e1552fc9f56c4aa6261ab51b469b2b1f19b3f6 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:22:59 +0200 Subject: [PATCH 06/14] raise_error: don't rely on module ordering in test --- tests/bugpoint/raise_error.ys | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/tests/bugpoint/raise_error.ys b/tests/bugpoint/raise_error.ys index 8fb10eb96..79127deff 100644 --- a/tests/bugpoint/raise_error.ys +++ b/tests/bugpoint/raise_error.ys @@ -22,34 +22,37 @@ logger -check-expected # raise_error with int exits with status design -load read +setattr -mod -unset raise_error def other +dump bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 7 select -assert-mod-count 1 =* select -assert-mod-count 1 top # raise_error -always still uses 'raise_error' attribute if possible design -load read +setattr -mod -unset raise_error def other bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -expect-return 7 select -assert-mod-count 1 =* select -assert-mod-count 1 top # raise_error with string prints message and exits with 1 design -load read -rename top abc +setattr -mod -unset raise_error top def bugpoint -suffix error -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1 select -assert-mod-count 1 =* select -assert-mod-count 1 other # raise_error with no value exits with 1 design -load read -rename def zzy +setattr -mod -unset raise_error top delete other bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 1 select -assert-mod-count 1 =* -select -assert-mod-count 1 zzy +select -assert-mod-count 1 def # raise_error -stderr prints to stderr and exits with 1 design -load read -rename top abc +setattr -mod -unset raise_error top def bugpoint -suffix error -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1 select -assert-mod-count 1 =* select -assert-mod-count 1 other From d7a80c6165eefd144aa5fd674b1039c021dd5125 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 19:19:57 +0200 Subject: [PATCH 07/14] write_rtlil: add -sort to match old behavior --- backends/rtlil/rtlil_backend.cc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 064bb7044..76276f01e 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -416,10 +416,14 @@ struct RTLILBackend : public Backend { log(" -selected\n"); log(" only write selected parts of the design.\n"); log("\n"); + log(" -sort\n"); + log(" sort design in-place (used to be default).\n"); + log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool selected = false; + bool do_sort = false; log_header(design, "Executing RTLIL backend.\n"); @@ -430,12 +434,19 @@ struct RTLILBackend : public Backend { selected = true; continue; } + if (arg == "-sort") { + do_sort = true; + continue; + } break; } extra_args(f, filename, args, argidx); log("Output filename: %s\n", filename.c_str()); + if (do_sort) + design->sort(); + *f << stringf("# Generated by %s\n", yosys_maybe_version()); RTLIL_BACKEND::dump_design(*f, design, selected, true, false); } From c12b485135f5924466f334e9816b07bf33ffd069 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 19:50:15 +0200 Subject: [PATCH 08/14] rtlil: add textual roundtrip test --- Makefile | 1 + tests/rtlil/.gitignore | 2 + tests/rtlil/everything.v | 40 + tests/rtlil/roundtrip-text.ref.il | 283 ++++++ tests/rtlil/roundtrip-text.sh | 30 + tests/rtlil/roundtrip-text.synth.ref.il | 1194 +++++++++++++++++++++++ tests/rtlil/run-test.sh | 4 + 7 files changed, 1554 insertions(+) create mode 100644 tests/rtlil/.gitignore create mode 100644 tests/rtlil/everything.v create mode 100644 tests/rtlil/roundtrip-text.ref.il create mode 100644 tests/rtlil/roundtrip-text.sh create mode 100644 tests/rtlil/roundtrip-text.synth.ref.il create mode 100755 tests/rtlil/run-test.sh diff --git a/Makefile b/Makefile index fb4fb5776..73421a5b7 100644 --- a/Makefile +++ b/Makefile @@ -874,6 +874,7 @@ MK_TEST_DIRS += tests/sim MK_TEST_DIRS += tests/svtypes MK_TEST_DIRS += tests/techmap MK_TEST_DIRS += tests/various +MK_TEST_DIRS += tests/rtlil ifeq ($(ENABLE_VERIFIC),1) ifneq ($(YOSYS_NOVERIFIC),1) MK_TEST_DIRS += tests/verific diff --git a/tests/rtlil/.gitignore b/tests/rtlil/.gitignore new file mode 100644 index 000000000..e1661c060 --- /dev/null +++ b/tests/rtlil/.gitignore @@ -0,0 +1,2 @@ +*.tmp.il +*.tmp.il.bak \ No newline at end of file diff --git a/tests/rtlil/everything.v b/tests/rtlil/everything.v new file mode 100644 index 000000000..666d630c2 --- /dev/null +++ b/tests/rtlil/everything.v @@ -0,0 +1,40 @@ +module alu( + input clk, + input [7:0] A, + input [7:0] B, + input [3:0] operation, + output reg [7:0] result, + output reg CF, + output reg ZF, + output reg SF +); + + localparam ALU_OP_ADD = 4'b0000; + localparam ALU_OP_SUB = 4'b0001; + + reg [8:0] tmp; + + always @(posedge clk) + begin + case (operation) + ALU_OP_ADD : + tmp = A + B; + ALU_OP_SUB : + tmp = A - B; + endcase + + CF <= tmp[8]; + ZF <= tmp[7:0] == 0; + SF <= tmp[7]; + + result <= tmp[7:0]; + end +endmodule + +module foo( + input [7:0] a, input [7:0] b, output [7:0] y +); + wire [7:0] bb; + assign b = bb; + assign y = a + bb; +endmodule diff --git a/tests/rtlil/roundtrip-text.ref.il b/tests/rtlil/roundtrip-text.ref.il new file mode 100644 index 000000000..d67cb3626 --- /dev/null +++ b/tests/rtlil/roundtrip-text.ref.il @@ -0,0 +1,283 @@ +autoidx 15 +attribute \src "everything.v:1.1-32.10" +attribute \cells_not_processed 1 +module \alu + attribute \src "everything.v:2.8-2.11" + wire input 1 \clk + attribute \src "everything.v:3.14-3.15" + wire width 8 input 2 \A + attribute \src "everything.v:4.14-4.15" + wire width 8 input 3 \B + attribute \src "everything.v:5.14-5.23" + wire width 4 input 4 \operation + attribute \src "everything.v:6.19-6.25" + wire width 8 output 5 \result + attribute \src "everything.v:7.13-7.15" + wire output 6 \CF + attribute \src "everything.v:8.13-8.15" + wire output 7 \ZF + attribute \src "everything.v:9.13-9.15" + wire output 8 \SF + attribute \src "everything.v:15.12-15.15" + wire width 9 \tmp + attribute \src "everything.v:17.2-31.5" + wire width 8 $0\result[7:0] + attribute \src "everything.v:17.2-31.5" + wire $0\CF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\ZF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\SF[0:0] + attribute \src "everything.v:17.2-31.5" + wire width 9 $0\tmp[8:0] + attribute \src "everything.v:17.2-31.5" + wire width 9 $1\tmp[8:0] + attribute \src "everything.v:21.11-21.16" + wire width 9 $add$everything.v:21$2_Y + attribute \src "everything.v:23.11-23.16" + wire width 9 $sub$everything.v:23$3_Y + attribute \src "everything.v:27.9-27.22" + wire $eq$everything.v:27$4_Y + attribute \src "everything.v:21.11-21.16" + cell $add $add$everything.v:21$2 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $add$everything.v:21$2_Y + end + attribute \src "everything.v:23.11-23.16" + cell $sub $sub$everything.v:23$3 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $sub$everything.v:23$3_Y + end + attribute \src "everything.v:27.9-27.22" + cell $eq $eq$everything.v:27$4 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A $1\tmp[8:0] [7:0] + connect \B 0 + connect \Y $eq$everything.v:27$4_Y + end + attribute \src "everything.v:17.2-31.5" + process $proc$everything.v:17$1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\tmp[8:0] $1\tmp[8:0] + assign $0\CF[0:0] $1\tmp[8:0] [8] + assign $0\ZF[0:0] $eq$everything.v:27$4_Y + assign $0\SF[0:0] $1\tmp[8:0] [7] + assign $0\result[7:0] $1\tmp[8:0] [7:0] + attribute \src "everything.v:19.3-24.10" + switch \operation + attribute \src "everything.v:19.19-19.19" + case 4'0000 + assign { } { } + assign $1\tmp[8:0] $add$everything.v:21$2_Y + attribute \src "everything.v:21.17-21.17" + case 4'0001 + assign { } { } + assign $1\tmp[8:0] $sub$everything.v:23$3_Y + case + assign $1\tmp[8:0] \tmp + end + sync posedge \clk + update \result $0\result[7:0] + update \CF $0\CF[0:0] + update \ZF $0\ZF[0:0] + update \SF $0\SF[0:0] + update \tmp $0\tmp[8:0] + end +end +attribute \src "everything.v:34.1-40.10" +attribute \cells_not_processed 1 +module \foo + attribute \src "everything.v:35.17-35.18" + wire width 8 input 1 \a + attribute \src "everything.v:35.32-35.33" + wire width 8 input 2 \b + attribute \src "everything.v:35.48-35.49" + wire width 8 output 3 \y + attribute \src "everything.v:37.16-37.18" + wire width 8 \bb + attribute \src "everything.v:39.16-39.22" + wire width 8 $add$everything.v:39$5_Y + attribute \src "everything.v:39.16-39.22" + cell $add $add$everything.v:39$5 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \a + connect \B \bb + connect \Y $add$everything.v:39$5_Y + end + connect \b \bb + connect \y $add$everything.v:39$5_Y +end +attribute \cells_not_processed 1 +attribute \src "everything.v:1.1-32.10" +module \zzz + attribute \src "everything.v:27.9-27.22" + wire $eq$everything.v:27$4_Y + attribute \src "everything.v:23.11-23.16" + wire width 9 $sub$everything.v:23$3_Y + attribute \src "everything.v:21.11-21.16" + wire width 9 $add$everything.v:21$2_Y + attribute \src "everything.v:17.2-31.5" + wire width 9 $1\tmp[8:0] + attribute \src "everything.v:17.2-31.5" + wire width 9 $0\tmp[8:0] + attribute \src "everything.v:17.2-31.5" + wire $0\SF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\ZF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\CF[0:0] + attribute \src "everything.v:17.2-31.5" + wire width 8 $0\result[7:0] + attribute \src "everything.v:15.12-15.15" + wire width 9 \tmp + attribute \src "everything.v:9.13-9.15" + wire output 8 \SF + attribute \src "everything.v:8.13-8.15" + wire output 7 \ZF + attribute \src "everything.v:7.13-7.15" + wire output 6 \CF + attribute \src "everything.v:6.19-6.25" + wire width 8 output 5 \result + attribute \src "everything.v:5.14-5.23" + wire width 4 input 4 \operation + attribute \src "everything.v:4.14-4.15" + wire width 8 input 3 \B + attribute \src "everything.v:3.14-3.15" + wire width 8 input 2 \A + attribute \src "everything.v:2.8-2.11" + wire input 1 \clk + wire $procmux$8_CMP + wire width 9 $procmux$7_Y + wire $procmux$9_CMP + attribute \src "everything.v:27.9-27.22" + cell $logic_not $eq$everything.v:27$4 + parameter \A_SIGNED 0 + parameter \Y_WIDTH 1 + parameter \A_WIDTH 8 + connect \A $1\tmp[8:0] [7:0] + connect \Y $eq$everything.v:27$4_Y + end + attribute \src "everything.v:23.11-23.16" + cell $sub $sub$everything.v:23$3 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $sub$everything.v:23$3_Y + end + attribute \src "everything.v:21.11-21.16" + cell $add $add$everything.v:21$2 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $add$everything.v:21$2_Y + end + attribute \src "everything.v:19.3-24.10" + attribute \full_case 1 + cell $eq $procmux$8_CMP0 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 4'0001 + connect \Y $procmux$8_CMP + end + attribute \src "everything.v:19.3-24.10" + attribute \full_case 1 + cell $pmux $procmux$7 + parameter \WIDTH 9 + parameter \S_WIDTH 2 + connect \A \tmp + connect \B { $add$everything.v:21$2_Y $sub$everything.v:23$3_Y } + connect \S { $procmux$9_CMP $procmux$8_CMP } + connect \Y $procmux$7_Y + end + attribute \src "everything.v:19.3-24.10" + attribute \full_case 1 + cell $logic_not $procmux$9_CMP0 + parameter \A_SIGNED 0 + parameter \Y_WIDTH 1 + parameter \A_WIDTH 4 + connect \A \operation + connect \Y $procmux$9_CMP + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$10 + parameter \WIDTH 8 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y [7:0] + connect \Q \result + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$11 + parameter \WIDTH 1 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y [8] + connect \Q \CF + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$12 + parameter \WIDTH 1 + parameter \CLK_POLARITY 1'1 + connect \D $eq$everything.v:27$4_Y + connect \Q \ZF + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$13 + parameter \WIDTH 1 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y [7] + connect \Q \SF + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$14 + parameter \WIDTH 9 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y + connect \Q \tmp + connect \CLK \clk + end + connect $0\result[7:0] $1\tmp[8:0] [7:0] + connect $0\SF[0:0] $1\tmp[8:0] [7] + connect $0\ZF[0:0] $eq$everything.v:27$4_Y + connect $0\CF[0:0] $1\tmp[8:0] [8] + connect $0\tmp[8:0] $1\tmp[8:0] + connect $1\tmp[8:0] $procmux$7_Y +end diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh new file mode 100644 index 000000000..7dd0327ca --- /dev/null +++ b/tests/rtlil/roundtrip-text.sh @@ -0,0 +1,30 @@ +set -euo pipefail +YS=../../yosys + +# write_rtlil and dump are equivalent +$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.write.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.dump.tmp.il +sed '/^$/d' -i.bak roundtrip-text.write.tmp.il +# Trim first line ("Generated by Yosys ...") +tail -n +2 roundtrip-text.write.tmp.il > roundtrip-text.write-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.write-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.ref.il + +# Loading and writing it out again doesn't change the RTLIL +$YS -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.reload.tmp.il +tail -n +2 roundtrip-text.reload.tmp.il > roundtrip-text.reload-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.reload-nogen.tmp.il + +# Hashing differences don't change the RTLIL +$YS --hash-seed=2345678 -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload-hash.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.reload-hash.tmp.il +tail -n +2 roundtrip-text.reload-hash.tmp.il > roundtrip-text.reload-hash-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.reload-hash-nogen.tmp.il + +echo "Without ABC, we don't get any irreproducibility and can pin that" +echo "Has this test case started failing for you? Consider updating the reference" +$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil roundtrip-text.synth.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.synth.tmp.il +tail -n +2 roundtrip-text.synth.tmp.il > roundtrip-text.synth-nogen.tmp.il +diff roundtrip-text.synth-nogen.tmp.il roundtrip-text.synth.ref.il diff --git a/tests/rtlil/roundtrip-text.synth.ref.il b/tests/rtlil/roundtrip-text.synth.ref.il new file mode 100644 index 000000000..04b27b1c1 --- /dev/null +++ b/tests/rtlil/roundtrip-text.synth.ref.il @@ -0,0 +1,1194 @@ +autoidx 511 +attribute \src "everything.v:34.1-40.10" +module \foo + attribute \src "everything.v:35.48-35.49" + wire width 8 output 3 \y + attribute \src "everything.v:37.16-37.18" + wire width 8 \bb + attribute \src "everything.v:35.32-35.33" + wire width 8 input 2 \b + attribute \src "everything.v:35.17-35.18" + wire width 8 input 1 \a + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + attribute \unused_bits "7" + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \force_downto 1 + wire width 8 $auto$alumacc.cc:495:replace_alu$21.lcu.G + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \force_downto 1 + wire width 8 $auto$alumacc.cc:495:replace_alu$21.X + attribute \unused_bits "7" + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \force_downto 1 + wire width 8 $auto$alumacc.cc:495:replace_alu$21.CO + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$219 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [6] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$218 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [4] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$217 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [2] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$216 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [5] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$213 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$211 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$210 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$209 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$207 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$206 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$205 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$204 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$201 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.X [4] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$200 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.X [2] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$197 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$195 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$194 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$193 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$138 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] + connect \B \b [6] + connect \A \a [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$137 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] + connect \B \b [5] + connect \A \a [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$136 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + connect \B \b [4] + connect \A \a [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$135 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] + connect \B \b [3] + connect \A \a [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$134 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + connect \B \b [2] + connect \A \a [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$133 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] + connect \B \b [1] + connect \A \a [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$132 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \B \b [0] + connect \A \a [0] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$131 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [7] + connect \B \b [7] + connect \A \a [7] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$130 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [6] + connect \B \b [6] + connect \A \a [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$129 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [5] + connect \B \b [5] + connect \A \a [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$128 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [4] + connect \B \b [4] + connect \A \a [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$127 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [3] + connect \B \b [3] + connect \A \a [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$126 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [2] + connect \B \b [2] + connect \A \a [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$125 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [1] + connect \B \b [1] + connect \A \a [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$124 + connect \Y \y [0] + connect \B \b [0] + connect \A \a [0] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$122 + connect \Y \y [7] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [6] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [7] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$121 + connect \Y \y [6] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$120 + connect \Y \y [5] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [4] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$119 + connect \Y \y [4] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$118 + connect \Y \y [3] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [2] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$117 + connect \Y \y [2] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$116 + connect \Y \y [1] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] + end + connect $auto$alumacc.cc:495:replace_alu$21.X [0] \y [0] + connect $auto$alumacc.cc:495:replace_alu$21.lcu.G [0] $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \bb \b +end +attribute \src "everything.v:1.1-32.10" +module \alu + attribute \src "everything.v:15.12-15.15" + wire width 9 \tmp + attribute \src "everything.v:6.19-6.25" + wire width 8 output 5 \result + attribute \src "everything.v:5.14-5.23" + wire width 4 input 4 \operation + attribute \src "everything.v:2.8-2.11" + wire input 1 \clk + attribute \src "everything.v:8.13-8.15" + wire output 7 \ZF + attribute \src "everything.v:9.13-9.15" + wire output 8 \SF + attribute \src "everything.v:7.13-7.15" + wire output 6 \CF + attribute \src "everything.v:4.14-4.15" + wire width 8 input 3 \B + attribute \src "everything.v:3.14-3.15" + wire width 8 input 2 \A + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \force_downto 1 + wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \force_downto 1 + wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \force_downto 1 + wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + wire $procmux$9_CMP + wire $procmux$8_CMP + wire $auto$simplemap.cc:254:simplemap_eqne$247 + wire $auto$simplemap.cc:166:logic_reduce$268 + wire width 2 $auto$simplemap.cc:166:logic_reduce$265 + wire $auto$simplemap.cc:166:logic_reduce$235 + wire width 2 $auto$simplemap.cc:166:logic_reduce$232 + wire width 4 $auto$simplemap.cc:166:logic_reduce$227 + wire width 2 $auto$simplemap.cc:125:simplemap_reduce$249 + wire $auto$rtlil.cc:3196:NotGate$497 + wire $auto$opt_dff.cc:247:make_patterns_logic$505 + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.lcu.G + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.X + attribute \unused_bits "8" + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.CO + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.BB + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:268.22-268.23" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.B + attribute \src "everything.v:17.2-31.5" + wire width 8 $0\result[7:0] + attribute \src "everything.v:17.2-31.5" + wire $0\ZF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\SF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\CF[0:0] + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$481 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$480 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$479 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$478 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$477 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$476 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$475 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$474 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$473 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$471 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$467 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$427 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$426 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$425 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$424 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$423 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$422 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$421 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$418 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [6] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$417 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [4] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$416 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [2] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$415 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [5] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$414 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [7] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y + end + attribute \src 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$techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$411 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$410 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$409 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$408 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:231.10-231.28" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$407 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [0] + connect \B $auto$alumacc.cc:495:replace_alu$18.X [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$405 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$404 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$403 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$402 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$401 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$400 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.X [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$399 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.X [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$398 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.X [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$397 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$396 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$395 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$394 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$393 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$392 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$391 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$326 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] + connect \A \A [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$325 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] + connect \A \A [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$324 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] + connect \A \A [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$323 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] + connect \A \A [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$322 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] + connect \A \A [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$321 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] + connect \A \A [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$320 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] + connect \A \A [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$319 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A \A [0] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$317 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [7] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] + connect \A \A [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$316 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [6] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] + connect \A \A [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$315 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [5] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] + connect \A \A [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$314 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [4] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] + connect \A \A [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$313 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [3] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] + connect \A \A [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$312 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [2] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] + connect \A \A [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$311 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] + connect \A \A [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$310 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [0] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A \A [0] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$308 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [8] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [7] + connect \A $auto$alumacc.cc:495:replace_alu$18.BB [8] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$307 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [7] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$306 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [6] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$305 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [5] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$304 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [4] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$303 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [3] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$302 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [2] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$301 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$464 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + connect \A \B [7] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$463 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + connect \A \B [6] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$462 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + connect \A \B [5] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$461 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + connect \A \B [4] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$460 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + connect \A \B [3] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$459 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + connect \A \B [2] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$458 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + connect \A \B [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$384 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [8] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [8] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$383 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [7] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$382 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$381 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [5] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$380 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$379 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [3] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$378 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$377 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [1] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$376 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A \B [0] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$299 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [8] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [8] + connect \A 1'0 + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$298 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [7] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] + connect \A \B [7] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$297 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [6] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] + connect \A \B [6] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$296 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [5] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] + connect \A \B [5] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$295 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [4] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] + connect \A \B [4] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$294 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [3] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] + connect \A \B [3] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$293 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [2] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] + connect \A \B [2] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$292 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [1] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] + connect \A \B [1] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$264 + connect \Y $0\CF[0:0] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [8] + connect \A 1'x + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$263 + connect \Y $0\SF[0:0] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [7] + connect \A \tmp [7] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$262 + connect \Y $0\result[7:0] [6] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [6] + connect \A \tmp [6] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$261 + connect \Y $0\result[7:0] [5] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [5] + connect \A \tmp [5] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$260 + connect \Y $0\result[7:0] [4] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [4] + connect \A \tmp [4] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$259 + connect \Y $0\result[7:0] [3] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [3] + connect \A \tmp [3] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$258 + connect \Y $0\result[7:0] [2] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [2] + connect \A \tmp [2] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$257 + connect \Y $0\result[7:0] [1] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [1] + connect \A \tmp [1] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$256 + connect \Y $0\result[7:0] [0] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [0] + connect \A \tmp [0] + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$270 + connect \Y $procmux$9_CMP + connect \A $auto$simplemap.cc:166:logic_reduce$268 + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$255 + connect \Y $procmux$8_CMP + connect \A $auto$simplemap.cc:254:simplemap_eqne$247 + end + attribute \src "everything.v:27.9-27.22" + cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$237 + connect \Y $0\ZF[0:0] + connect \A $auto$simplemap.cc:166:logic_reduce$235 + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$269 + connect \Y $auto$simplemap.cc:166:logic_reduce$268 + connect \B $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect \A $auto$simplemap.cc:166:logic_reduce$265 [0] + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$267 + connect \Y $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect \B \operation [3] + connect \A \operation [2] + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$266 + connect \Y $auto$simplemap.cc:166:logic_reduce$265 [0] + connect \B \operation [1] + connect \A \operation [0] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$236 + connect \Y $auto$simplemap.cc:166:logic_reduce$235 + connect \B $auto$simplemap.cc:166:logic_reduce$232 [1] + connect \A $auto$simplemap.cc:166:logic_reduce$232 [0] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$234 + connect \Y $auto$simplemap.cc:166:logic_reduce$232 [1] + connect \B $auto$simplemap.cc:166:logic_reduce$227 [3] + connect \A $auto$simplemap.cc:166:logic_reduce$227 [2] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$233 + connect \Y $auto$simplemap.cc:166:logic_reduce$232 [0] + connect \B $auto$simplemap.cc:166:logic_reduce$227 [1] + connect \A $auto$simplemap.cc:166:logic_reduce$227 [0] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$231 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [3] + connect \B $0\SF[0:0] + connect \A $0\result[7:0] [6] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$230 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [2] + connect \B $0\result[7:0] [5] + connect \A $0\result[7:0] [4] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$229 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [1] + connect \B $0\result[7:0] [3] + connect \A $0\result[7:0] [2] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$228 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [0] + connect \B $0\result[7:0] [1] + connect \A $0\result[7:0] [0] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$253 + connect \Y $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect \A $auto$simplemap.cc:125:simplemap_reduce$249 [0] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$250 + connect \Y $auto$simplemap.cc:125:simplemap_reduce$249 [0] + connect \B \operation [1] + connect \A $auto$rtlil.cc:3196:NotGate$497 + end + attribute \src 0'x + cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$226 + connect \Y $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $procmux$9_CMP + connect \A $procmux$8_CMP + end + cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$502 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [8] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] + end + cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$500 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [0] + end + cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$496 + connect \Y $auto$rtlil.cc:3196:NotGate$497 + connect \A \operation [0] + end + attribute \src "everything.v:17.2-31.5" + cell $_DFFE_PP_ $auto$ff.cc:266:slice$504 + connect \Q \CF + connect \E $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \D $0\CF[0:0] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$289 + connect \Q \tmp [7] + connect \D $0\SF[0:0] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$288 + connect \Q \tmp [6] + connect \D $0\result[7:0] [6] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$287 + connect \Q \tmp [5] + connect \D $0\result[7:0] [5] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$286 + connect \Q \tmp [4] + connect \D $0\result[7:0] [4] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$285 + connect \Q \tmp [3] + connect \D $0\result[7:0] [3] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$284 + connect \Q \tmp [2] + connect \D $0\result[7:0] [2] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$283 + connect \Q \tmp [1] + connect \D $0\result[7:0] [1] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$282 + connect \Q \tmp [0] + connect \D $0\result[7:0] [0] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$280 + connect \Q \ZF + connect \D $0\ZF[0:0] + connect \C \clk + end + connect $0\result[7:0] [7] $0\SF[0:0] + connect $auto$alumacc.cc:495:replace_alu$18.B [0] \B [0] + connect $auto$alumacc.cc:495:replace_alu$18.X [8] $auto$alumacc.cc:495:replace_alu$18.BB [8] + connect $auto$alumacc.cc:495:replace_alu$18.lcu.G [8] 1'0 + connect $auto$simplemap.cc:166:logic_reduce$265 [1] $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [8] $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [0] } { 1'1 $auto$alumacc.cc:495:replace_alu$18.BB [0] } + connect { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [7] $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [0] } { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] $auto$alumacc.cc:495:replace_alu$18.BB [0] } + connect $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [0] \B [0] + connect \SF \tmp [7] + connect \result \tmp [7:0] + connect \tmp [8] \CF +end diff --git a/tests/rtlil/run-test.sh b/tests/rtlil/run-test.sh new file mode 100755 index 000000000..70b282a9a --- /dev/null +++ b/tests/rtlil/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../gen-tests-makefile.sh +generate_mk --bash From 4fb0db4d693463b9eb1013769fd648d3c25c435b Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 19:56:28 +0200 Subject: [PATCH 09/14] rtlil: add roundtrip test for design -stash and design -save, fix #5321 --- kernel/rtlil.cc | 1 + tests/rtlil/roundtrip-design.sh | 8 ++++++++ tests/rtlil/roundtrip-text.ref.il | 6 +++--- 3 files changed, 12 insertions(+), 3 deletions(-) create mode 100644 tests/rtlil/roundtrip-design.sh diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 0250346d1..4e07a473d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -5855,6 +5855,7 @@ RTLIL::CaseRule *RTLIL::CaseRule::clone() const RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule; new_caserule->compare = compare; new_caserule->actions = actions; + new_caserule->attributes = attributes; for (auto &it : switches) new_caserule->switches.push_back(it->clone()); return new_caserule; diff --git a/tests/rtlil/roundtrip-design.sh b/tests/rtlil/roundtrip-design.sh new file mode 100644 index 000000000..beacddd8f --- /dev/null +++ b/tests/rtlil/roundtrip-design.sh @@ -0,0 +1,8 @@ +set -euo pipefail +YS=../../yosys + +$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-push.tmp.il; design -push; design -pop; write_rtlil roundtrip-design-pop.tmp.il" +diff roundtrip-design-push.tmp.il roundtrip-design-pop.tmp.il + +$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-save.tmp.il; design -save foo; design -load foo; write_rtlil roundtrip-design-load.tmp.il" +diff roundtrip-design-save.tmp.il roundtrip-design-load.tmp.il diff --git a/tests/rtlil/roundtrip-text.ref.il b/tests/rtlil/roundtrip-text.ref.il index d67cb3626..cc45f53dd 100644 --- a/tests/rtlil/roundtrip-text.ref.il +++ b/tests/rtlil/roundtrip-text.ref.il @@ -203,7 +203,7 @@ module \zzz connect \B \B connect \Y $add$everything.v:21$2_Y end - attribute \src "everything.v:19.3-24.10" + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" attribute \full_case 1 cell $eq $procmux$8_CMP0 parameter \A_SIGNED 0 @@ -215,7 +215,7 @@ module \zzz connect \B 4'0001 connect \Y $procmux$8_CMP end - attribute \src "everything.v:19.3-24.10" + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" attribute \full_case 1 cell $pmux $procmux$7 parameter \WIDTH 9 @@ -225,7 +225,7 @@ module \zzz connect \S { $procmux$9_CMP $procmux$8_CMP } connect \Y $procmux$7_Y end - attribute \src "everything.v:19.3-24.10" + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" attribute \full_case 1 cell $logic_not $procmux$9_CMP0 parameter \A_SIGNED 0 From c48e6d41eb347225bc688ee7398f0f45db6d3641 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 20:36:31 +0200 Subject: [PATCH 10/14] rtlil: move test temporary files to temp directory --- tests/rtlil/.gitignore | 3 +-- tests/rtlil/roundtrip-design.sh | 10 +++++---- tests/rtlil/roundtrip-text.sh | 38 +++++++++++++++++---------------- 3 files changed, 27 insertions(+), 24 deletions(-) diff --git a/tests/rtlil/.gitignore b/tests/rtlil/.gitignore index e1661c060..abe251a76 100644 --- a/tests/rtlil/.gitignore +++ b/tests/rtlil/.gitignore @@ -1,2 +1 @@ -*.tmp.il -*.tmp.il.bak \ No newline at end of file +/temp \ No newline at end of file diff --git a/tests/rtlil/roundtrip-design.sh b/tests/rtlil/roundtrip-design.sh index beacddd8f..018e363c7 100644 --- a/tests/rtlil/roundtrip-design.sh +++ b/tests/rtlil/roundtrip-design.sh @@ -1,8 +1,10 @@ set -euo pipefail YS=../../yosys -$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-push.tmp.il; design -push; design -pop; write_rtlil roundtrip-design-pop.tmp.il" -diff roundtrip-design-push.tmp.il roundtrip-design-pop.tmp.il +mkdir -p temp -$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-save.tmp.il; design -save foo; design -load foo; write_rtlil roundtrip-design-load.tmp.il" -diff roundtrip-design-save.tmp.il roundtrip-design-load.tmp.il +$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il" +diff temp/roundtrip-design-push.il temp/roundtrip-design-pop.il + +$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il" +diff temp/roundtrip-design-save.il temp/roundtrip-design-load.il diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index 7dd0327ca..45db7ee72 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -1,30 +1,32 @@ set -euo pipefail YS=../../yosys +mkdir -p temp + # write_rtlil and dump are equivalent -$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.write.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.dump.tmp.il -sed '/^$/d' -i.bak roundtrip-text.write.tmp.il +$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il" +sed '/^$/d' -i.bak temp/roundtrip-text.dump.il +sed '/^$/d' -i.bak temp/roundtrip-text.write.il # Trim first line ("Generated by Yosys ...") -tail -n +2 roundtrip-text.write.tmp.il > roundtrip-text.write-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.write-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.ref.il +tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il +diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il +diff temp/roundtrip-text.dump.il roundtrip-text.ref.il # Loading and writing it out again doesn't change the RTLIL -$YS -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.reload.tmp.il -tail -n +2 roundtrip-text.reload.tmp.il > roundtrip-text.reload-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.reload-nogen.tmp.il +$YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" +sed '/^$/d' -i.bak temp/roundtrip-text.reload.il +tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il +diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il # Hashing differences don't change the RTLIL -$YS --hash-seed=2345678 -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload-hash.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.reload-hash.tmp.il -tail -n +2 roundtrip-text.reload-hash.tmp.il > roundtrip-text.reload-hash-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.reload-hash-nogen.tmp.il +$YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il" +sed '/^$/d' -i.bak temp/roundtrip-text.reload-hash.il +tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il +diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il echo "Without ABC, we don't get any irreproducibility and can pin that" echo "Has this test case started failing for you? Consider updating the reference" -$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil roundtrip-text.synth.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.synth.tmp.il -tail -n +2 roundtrip-text.synth.tmp.il > roundtrip-text.synth-nogen.tmp.il -diff roundtrip-text.synth-nogen.tmp.il roundtrip-text.synth.ref.il +$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil temp/roundtrip-text.synth.il" +sed '/^$/d' -i.bak temp/roundtrip-text.synth.il +tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il +diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il From 6c4d00ca7a86392989b500c3e28d010fa595d187 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 20:43:52 +0200 Subject: [PATCH 11/14] functional: in test, rely less on wreduce doing a perfect job --- tests/functional/test_functional.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 7a09966d8..d4ebc3484 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args): run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)]) def yosys_synth(verilog_file, rtlil_file): - yosys(f"read_verilog {quote(verilog_file)} ; prep ; write_rtlil {quote(rtlil_file)}") + yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven ; write_rtlil {quote(rtlil_file)}") # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): @@ -91,4 +91,4 @@ def test_print_graph(tmp_path): tb_file = base_path / 'tests/functional/picorv32_tb.v' cpu_file = base_path / 'tests/functional/picorv32.v' # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl - yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; clk2fflogic; test_generic") + yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven ; flatten; clk2fflogic; test_generic") From f8630d07776f5abdbecaa7c9936bb75fab40e4ef Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Sep 2025 01:57:17 +0200 Subject: [PATCH 12/14] read_verilog: add -relativeshare for synthesis reproducibility testing --- frontends/verilog/verilog_frontend.cc | 17 +++++++++++++++ passes/techmap/techmap.cc | 9 ++++++++ techlibs/common/synth.cc | 30 ++++++++++++++++++++------- techlibs/fabulous/synth_fabulous.cc | 2 +- tests/functional/test_functional.py | 4 ++-- 5 files changed, 51 insertions(+), 11 deletions(-) diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 4b4f7ad8d..b24a10328 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -229,6 +229,10 @@ struct VerilogFrontend : public Frontend { log(" add 'dir' to the directories which are used when searching include\n"); log(" files\n"); log("\n"); + log(" -relativeshare\n"); + log(" use paths relative to share directory for source locations\n"); + log(" where possible (experimental).\n"); + log("\n"); log("The command 'verilog_defaults' can be used to register default options for\n"); log("subsequent calls to 'read_verilog'.\n"); log("\n"); @@ -273,6 +277,7 @@ struct VerilogFrontend : public Frontend { bool flag_nowb = false; bool flag_nosynthesis = false; bool flag_yydebug = false; + bool flag_relative_share = false; define_map_t defines_map; std::list include_dirs; @@ -450,6 +455,11 @@ struct VerilogFrontend : public Frontend { attributes.push_back(RTLIL::escape_id(args[++argidx])); continue; } + if (arg == "-relativeshare") { + flag_relative_share = true; + log_experimental("read_verilog -relativeshare"); + continue; + } if (arg == "-D" && argidx+1 < args.size()) { std::string name = args[++argidx], value; size_t equal = name.find('='); @@ -490,6 +500,13 @@ struct VerilogFrontend : public Frontend { log("Parsing %s%s input from `%s' to AST representation.\n", parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str()); + log("verilog frontend filename %s\n", filename.c_str()); + if (flag_relative_share) { + auto share_path = proc_share_dirname(); + if (filename.substr(0, share_path.length()) == share_path) + filename = std::string("+/") + filename.substr(share_path.length()); + log("new filename %s\n", filename.c_str()); + } AST::sv_mode_but_global_and_used_for_literally_one_condition = parse_mode.sv; std::string code_after_preproc; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 95c733f62..b5a66f3a7 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1031,6 +1031,10 @@ struct TechmapPass : public Pass { log(" -dont_map \n"); log(" leave the given cell type unmapped by ignoring any mapping rules for it\n"); log("\n"); + log(" -relativeshare\n"); + log(" use paths relative to share directory for source locations\n"); + log(" where possible (experimental).\n"); + log("\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("match cells with a type that match the text value of this attribute. Otherwise\n"); log("the module name will be used to match the cell. Multiple space-separated cell\n"); @@ -1184,6 +1188,11 @@ struct TechmapPass : public Pass { verilog_frontend += " -I " + args[++argidx]; continue; } + if (args[argidx] == "-relativeshare") { + verilog_frontend += " -relativeshare"; + log_experimental("techmap -relativeshare"); + continue; + } if (args[argidx] == "-assert") { worker.assert_mode = true; continue; diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 8b4561c34..d63f5c688 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -98,13 +98,17 @@ struct SynthPass : public ScriptPass { log(" mapping library in the `techmap` step. this option can be\n"); log(" repeated.\n"); log("\n"); + log(" -relativeshare\n"); + log(" use paths relative to share directory for source locations\n"); + log(" where possible (experimental).\n"); + log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } string top_module, fsm_opts, memory_opts, abc; - bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt; + bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt, relative_share; int lut; std::vector techmap_maps; @@ -124,6 +128,7 @@ struct SynthPass : public ScriptPass { flowmap = false; booth = false; hieropt = false; + relative_share = false; abc = "abc"; techmap_maps.clear(); } @@ -211,6 +216,11 @@ struct SynthPass : public ScriptPass { hieropt = true; continue; } + if (args[argidx] == "-relativeshare") { + relative_share = true; + log_experimental("synth -relativeshare"); + continue; + } break; } extra_args(args, argidx, design); @@ -239,6 +249,10 @@ struct SynthPass : public ScriptPass { else hieropt_flag = hieropt ? " -hier" : ""; + std::string techmap_cmd = "techmap"; + if (relative_share) + techmap_cmd += " -relativeshare"; + if (check_label("begin")) { if (help_mode) { run("hierarchy -check [-top | -auto-top]"); @@ -268,9 +282,9 @@ struct SynthPass : public ScriptPass { run("peepopt"); run("opt_clean"); if (help_mode) - run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); + run(techmap_cmd + " -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); else if (lut) - run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut)); + run(stringf("%s -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", techmap_cmd, lut)); if (booth || help_mode) run("booth", " (if -booth)"); if (!noalumacc) @@ -287,22 +301,22 @@ struct SynthPass : public ScriptPass { run("memory_map"); run("opt -full"); if (help_mode) { - run("techmap", " (unless -extra-map)"); - run("techmap -map +/techmap.v -map ", " (if -extra-map)"); + run(techmap_cmd, " (unless -extra-map)"); + run(techmap_cmd + " -map +/techmap.v -map ", " (if -extra-map)"); } else { std::string techmap_opts; if (!techmap_maps.empty()) techmap_opts += " -map +/techmap.v"; for (auto fn : techmap_maps) techmap_opts += stringf(" -map %s", fn.c_str()); - run("techmap" + techmap_opts); + run(techmap_cmd + techmap_opts); } if (help_mode) { - run("techmap -map +/gate2lut.v", "(if -noabc and -lut)"); + run(techmap_cmd + " -map +/gate2lut.v", "(if -noabc and -lut)"); run("clean; opt_lut", " (if -noabc and -lut)"); run("flowmap -maxlut K", " (if -flowmap and -lut)"); } else if (noabc && lut) { - run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut)); + run(stringf("%s -map +/gate2lut.v -D LUT_WIDTH=%d", techmap_cmd, lut)); run("clean; opt_lut"); } else if (flowmap) { run(stringf("flowmap -maxlut %d", lut)); diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 8d2fb1471..9c4f142ba 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -69,7 +69,7 @@ struct SynthPass : public ScriptPass log(" use the specified Verilog file for extra primitives (can be specified multiple\n"); log(" times).\n"); log("\n"); - log(" -extra-map \n"); + log(" -extra-map \n"); log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n"); log(" times).\n"); log("\n"); diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index d4ebc3484..e4c78a1fb 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args): run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)]) def yosys_synth(verilog_file, rtlil_file): - yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven ; write_rtlil {quote(rtlil_file)}") + yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven -undef ; write_rtlil {quote(rtlil_file)}") # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): @@ -91,4 +91,4 @@ def test_print_graph(tmp_path): tb_file = base_path / 'tests/functional/picorv32_tb.v' cpu_file = base_path / 'tests/functional/picorv32.v' # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl - yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven ; flatten; clk2fflogic; test_generic") + yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven -undef ; flatten; clk2fflogic; test_generic") From 08d79595cc0c17c4ea43120a3094d70ee27d0cf7 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Sep 2025 01:58:08 +0200 Subject: [PATCH 13/14] rtlil: fix roundtrip test by eliminating absolute paths from src attributes with -relativeshare --- tests/rtlil/roundtrip-text.sh | 2 +- tests/rtlil/roundtrip-text.synth.ref.il | 562 ++++++++++++------------ 2 files changed, 282 insertions(+), 282 deletions(-) diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index 45db7ee72..c475a9d9a 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -26,7 +26,7 @@ diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il echo "Without ABC, we don't get any irreproducibility and can pin that" echo "Has this test case started failing for you? Consider updating the reference" -$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil temp/roundtrip-text.synth.il" +$YS -p "read_verilog -sv everything.v; synth -relativeshare -noabc; write_rtlil temp/roundtrip-text.synth.il" sed '/^$/d' -i.bak temp/roundtrip-text.synth.il tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il diff --git a/tests/rtlil/roundtrip-text.synth.ref.il b/tests/rtlil/roundtrip-text.synth.ref.il index 04b27b1c1..ab48affc6 100644 --- a/tests/rtlil/roundtrip-text.synth.ref.il +++ b/tests/rtlil/roundtrip-text.synth.ref.il @@ -9,276 +9,276 @@ module \foo wire width 8 input 2 \b attribute \src "everything.v:35.17-35.18" wire width 8 input 1 \a - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y attribute \unused_bits "7" - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" attribute \force_downto 1 wire width 8 $auto$alumacc.cc:495:replace_alu$21.lcu.G - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \src "everything.v:39.16-39.22|+/techmap.v:270.23-270.24" attribute \force_downto 1 wire width 8 $auto$alumacc.cc:495:replace_alu$21.X attribute \unused_bits "7" - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:274.23-274.25" attribute \force_downto 1 wire width 8 $auto$alumacc.cc:495:replace_alu$21.CO - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$219 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [6] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$218 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [4] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$217 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [2] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$216 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [5] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$213 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$211 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$210 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$209 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$207 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$206 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$205 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$204 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$201 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y connect \B $auto$alumacc.cc:495:replace_alu$21.X [4] connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$200 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y connect \B $auto$alumacc.cc:495:replace_alu$21.X [2] connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$197 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$195 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$194 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$193 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$138 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] connect \B \b [6] connect \A \a [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$137 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] connect \B \b [5] connect \A \a [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$136 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] connect \B \b [4] connect \A \a [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$135 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] connect \B \b [3] connect \A \a [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$134 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] connect \B \b [2] connect \A \a [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$133 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] connect \B \b [1] connect \A \a [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$132 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [0] connect \B \b [0] connect \A \a [0] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$131 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [7] connect \B \b [7] connect \A \a [7] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$130 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [6] connect \B \b [6] connect \A \a [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$129 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [5] connect \B \b [5] connect \A \a [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$128 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [4] connect \B \b [4] connect \A \a [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$127 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [3] connect \B \b [3] connect \A \a [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$126 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [2] connect \B \b [2] connect \A \a [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$125 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [1] connect \B \b [1] connect \A \a [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$124 connect \Y \y [0] connect \B \b [0] connect \A \a [0] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$122 connect \Y \y [7] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [6] connect \A $auto$alumacc.cc:495:replace_alu$21.X [7] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$121 connect \Y \y [6] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$120 connect \Y \y [5] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [4] connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$119 connect \Y \y [4] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$118 connect \Y \y [3] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [2] connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$117 connect \Y \y [2] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$116 connect \Y \y [1] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] @@ -308,61 +308,61 @@ module \alu wire width 8 input 3 \B attribute \src "everything.v:3.14-3.15" wire width 8 input 2 \A - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y + attribute \src "+/techmap.v:270.26-270.27" attribute \force_downto 1 wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \src "+/techmap.v:274.23-274.25" attribute \force_downto 1 wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \src "+/techmap.v:279.21-279.23" attribute \force_downto 1 wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y wire $procmux$9_CMP wire $procmux$8_CMP wire $auto$simplemap.cc:254:simplemap_eqne$247 @@ -374,23 +374,23 @@ module \alu wire width 2 $auto$simplemap.cc:125:simplemap_reduce$249 wire $auto$rtlil.cc:3196:NotGate$497 wire $auto$opt_dff.cc:247:make_patterns_logic$505 - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.lcu.G - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \src "everything.v:23.11-23.16|+/techmap.v:270.26-270.27" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \src "everything.v:23.11-23.16|+/techmap.v:270.23-270.24" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.X attribute \unused_bits "8" - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:274.23-274.25" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.CO - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.21-279.23" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.BB - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:268.22-268.23" + attribute \src "everything.v:23.11-23.16|+/techmap.v:268.22-268.23" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.B attribute \src "everything.v:17.2-31.5" @@ -401,496 +401,496 @@ module \alu wire $0\SF[0:0] attribute \src "everything.v:17.2-31.5" wire $0\CF[0:0] - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$481 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$480 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$479 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$478 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$477 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y + connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$476 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$475 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$474 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$473 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$471 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$467 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$427 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$426 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$425 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$424 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$423 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$422 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$421 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$418 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [6] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$417 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [4] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$416 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [2] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$415 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [5] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$414 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [7] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$413 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$412 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$411 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$410 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$409 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$408 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:231.10-231.28" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:231.10-231.28" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$407 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [0] connect \B $auto$alumacc.cc:495:replace_alu$18.X [0] connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$405 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$404 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$403 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$402 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$401 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$400 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y connect \B $auto$alumacc.cc:495:replace_alu$18.X [6] connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$399 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y connect \B $auto$alumacc.cc:495:replace_alu$18.X [4] connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$398 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y connect \B $auto$alumacc.cc:495:replace_alu$18.X [2] connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$397 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$396 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$395 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$394 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$393 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$392 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$391 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$326 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] connect \A \A [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$325 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] connect \A \A [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$324 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] connect \A \A [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$323 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] connect \A \A [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$322 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] connect \A \A [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$321 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] connect \A \A [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$320 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] connect \A \A [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$319 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A \A [0] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$317 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [7] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] connect \A \A [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$316 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [6] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] connect \A \A [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$315 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [5] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] connect \A \A [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$314 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [4] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] connect \A \A [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$313 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [3] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] connect \A \A [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$312 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [2] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] connect \A \A [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$311 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] connect \A \A [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$310 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [0] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A \A [0] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$308 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [8] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [7] connect \A $auto$alumacc.cc:495:replace_alu$18.BB [8] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$307 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [7] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [6] connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$306 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [6] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$305 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [5] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [4] connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$304 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [4] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$303 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [3] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [2] connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$302 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [2] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$301 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [1] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$464 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] connect \A \B [7] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$463 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] connect \A \B [6] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$462 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] connect \A \B [5] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$461 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] connect \A \B [4] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$460 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] connect \A \B [3] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$459 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] connect \A \B [2] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$458 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] connect \A \B [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$384 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [8] connect \A $auto$alumacc.cc:495:replace_alu$18.B [8] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$383 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [7] connect \A $auto$alumacc.cc:495:replace_alu$18.B [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$382 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [6] connect \A $auto$alumacc.cc:495:replace_alu$18.B [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$381 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [5] connect \A $auto$alumacc.cc:495:replace_alu$18.B [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$380 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [4] connect \A $auto$alumacc.cc:495:replace_alu$18.B [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$379 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [3] connect \A $auto$alumacc.cc:495:replace_alu$18.B [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$378 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [2] connect \A $auto$alumacc.cc:495:replace_alu$18.B [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$377 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [1] connect \A $auto$alumacc.cc:495:replace_alu$18.B [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$376 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A \B [0] From 9de931b902801461a1f0498cab268b8597d4fae0 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Sep 2025 15:42:57 +0200 Subject: [PATCH 14/14] rtlil: fix roundtrip test on macOS due to sed non-POSIX non-sense --- tests/rtlil/roundtrip-text.sh | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index c475a9d9a..7a979879c 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -3,10 +3,17 @@ YS=../../yosys mkdir -p temp +# non-POSIX sed -i inconsistency workaround +remove_empty_lines() { + local file="$1" + sed '/^$/d' "$file" > temp/tmp + mv temp/tmp "$file" +} + # write_rtlil and dump are equivalent $YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il" -sed '/^$/d' -i.bak temp/roundtrip-text.dump.il -sed '/^$/d' -i.bak temp/roundtrip-text.write.il +remove_empty_lines temp/roundtrip-text.dump.il +remove_empty_lines temp/roundtrip-text.write.il # Trim first line ("Generated by Yosys ...") tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il @@ -14,19 +21,19 @@ diff temp/roundtrip-text.dump.il roundtrip-text.ref.il # Loading and writing it out again doesn't change the RTLIL $YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" -sed '/^$/d' -i.bak temp/roundtrip-text.reload.il +remove_empty_lines temp/roundtrip-text.reload.il tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il # Hashing differences don't change the RTLIL $YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il" -sed '/^$/d' -i.bak temp/roundtrip-text.reload-hash.il +remove_empty_lines temp/roundtrip-text.reload-hash.il tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il echo "Without ABC, we don't get any irreproducibility and can pin that" echo "Has this test case started failing for you? Consider updating the reference" $YS -p "read_verilog -sv everything.v; synth -relativeshare -noabc; write_rtlil temp/roundtrip-text.synth.il" -sed '/^$/d' -i.bak temp/roundtrip-text.synth.il +remove_empty_lines temp/roundtrip-text.synth.il tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il