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Merge 9814f9dc4f into 17ca71e1ab

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gatin00b 2025-12-24 21:05:31 +00:00 • committed by GitHub
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20
tests/verilog/genblk_wire.sv Normal file
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module gold(a, b);
output wire [1:0] a;
input wire [1:0] b;
genvar i;
for (i = 0; i < 2; i++) begin
wire x;
assign x = b[i];
assign a[i] = x;
end
endmodule
module gate(a, b);
output wire [1:0] a;
input wire [1:0] b;
genvar i;
for (i = 0; i < 2; i++) begin
assign x = b[i];
assign a[i] = x;
end
endmodule

17
tests/verilog/genblk_wire.ys Normal file
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logger -expect warning "Identifier `\\genblk1[[]0[]]\.x' is implicitly declared." 1
logger -expect warning "Identifier `\\genblk1[[]1[]]\.x' is implicitly declared." 1
read_verilog -sv genblk_wire.sv
logger -check-expected
select -assert-count 1 gate/genblk1[0].x
select -assert-count 1 gate/genblk1[1].x
select -assert-count 0 gate/genblk1[2].x
select -assert-count 1 gold/genblk1[0].x
select -assert-count 1 gold/genblk1[1].x
select -assert-count 0 gold/genblk1[2].x
proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert