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Fix sign extension when sign is 1'bx

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This commit is contained in:
Eddie Hung 2019-06-20 10:04:42 -07:00
parent 477e566e8d
commit 0221f3e1c5
1 changed files with 1 additions and 1 deletions
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2
kernel/rtlil.cc
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@ -3437,7 +3437,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
if (width_ < width) { if (width_ < width) {
RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx; RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
if (!is_signed) if (padding != RTLIL::State::Sx && !is_signed)
padding = RTLIL::State::S0; padding = RTLIL::State::S0;
while (width_ < width) while (width_ < width)
append(padding); append(padding);