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Merge pull request #2257 from antmicro/fix-conflicts

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Restore #2203 and #2244 and fix parser conflicts
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clairexen 2020-07-15 11:49:09 +02:00 • committed by GitHub
commit 021ce8e596
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5 changed files with 59 additions and 9 deletions
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6
tests/various/integer_range_bad_syntax.ys Normal file
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logger -expect error "syntax error, unexpected" 1
read_verilog -sv <<EOT
module test_integer_range();
parameter integer [31:0] a = 0;
endmodule
EOT

6
tests/various/integer_real_bad_syntax.ys Normal file
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logger -expect error "syntax error, unexpected TOK_REAL" 1
read_verilog -sv <<EOT
module test_integer_real();
parameter integer real a = 0;
endmodule
EOT

9
tests/various/logic_param_simple.ys Normal file
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read_verilog -sv <<EOT
module test_logic_param();
parameter logic a = 0;
parameter logic [31:0] e = 0;
parameter logic signed b = 0;
parameter logic unsigned c = 0;
parameter logic unsigned [31:0] d = 0;
endmodule
EOT

28
tests/various/signed.ys Normal file
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# SV LRM A2.2.1
read_verilog -sv <<EOT
module test_signed();
parameter integer signed a = 0;
parameter integer unsigned b = 0;
endmodule
EOT
design -reset
read_verilog -sv <<EOT
module test_signed();
parameter logic signed [7:0] a = 0;
parameter logic unsigned [7:0] b = 0;
endmodule
EOT
design -reset
logger -expect error "syntax error, unexpected TOK_INTEGER" 1
read_verilog -sv <<EOT
module test_signed();
parameter signed integer a = 0;
parameter unsigned integer b = 0;
endmodule
EOT