From 8f9a0b680a7be1e5e8807d646bc79e2b08015eef Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Sat, 16 Nov 2024 22:56:41 -0800 Subject: [PATCH 1/3] Fix O(N^2) port dump down to O(N) --- backends/verilog/verilog_backend.cc | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 04b87b40d..6a81a31c9 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2334,17 +2334,23 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); bool keep_running = true; int cnt = 0; - for (int port_id = 1; keep_running; port_id++) { - keep_running = false; - for (auto wire : module->wires()) { - if (wire->port_id == port_id) { - if (port_id != 1) - f << stringf(", "); - f << stringf("%s", id(wire->name).c_str()); - keep_running = true; - if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++; - continue; - } + int max_port_id = 0; + for (auto wire : module->wires()) { + max_port_id = std::max(wire->port_id, max_port_id); + } + std::vector wires(max_port_id + 1, nullptr); + for (auto wire : module->wires()) { + wires[wire->port_id] = wire; + } + for (int port_id = 1; port_id <= max_port_id; port_id++) { + Wire *wire = wires[port_id]; + if (wire) { + if (port_id != 1) + f << stringf(", "); + f << stringf("%s", id(wire->name).c_str()); + keep_running = true; + if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++; + continue; } } f << stringf(");\n"); From 3a327293731351aafb87349b5ea8064bd8e8a1ac Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Sun, 17 Nov 2024 10:40:04 -0800 Subject: [PATCH 2/3] Remove keep_running variable (unused) --- backends/verilog/verilog_backend.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6a81a31c9..6602d96d7 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2332,7 +2332,6 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); - bool keep_running = true; int cnt = 0; int max_port_id = 0; for (auto wire : module->wires()) { @@ -2348,7 +2347,6 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) if (port_id != 1) f << stringf(", "); f << stringf("%s", id(wire->name).c_str()); - keep_running = true; if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++; continue; } From ace558e90c5a29179bf0d624057e433911ebb08a Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Sun, 17 Nov 2024 11:36:30 -0800 Subject: [PATCH 3/3] Simplify using module->ports, which is apparently sorted --- backends/verilog/verilog_backend.cc | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6602d96d7..a8dd356bc 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2333,18 +2333,10 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); int cnt = 0; - int max_port_id = 0; - for (auto wire : module->wires()) { - max_port_id = std::max(wire->port_id, max_port_id); - } - std::vector wires(max_port_id + 1, nullptr); - for (auto wire : module->wires()) { - wires[wire->port_id] = wire; - } - for (int port_id = 1; port_id <= max_port_id; port_id++) { - Wire *wire = wires[port_id]; + for (auto port : module->ports) { + Wire *wire = module->wire(port); if (wire) { - if (port_id != 1) + if (port != module->ports[0]) f << stringf(", "); f << stringf("%s", id(wire->name).c_str()); if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;