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Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required
This commit is contained in:
Eddie Hung
commit
020606f81c
91 changed files with 3417 additions and 2460 deletions
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@ -325,6 +325,7 @@ endmodule
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
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(* abc9_box_id=1100, lib_whitebox, abc9_flop *)
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module FDRE (
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(* abc9_arrival=303 *)
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output reg Q,
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@ -348,6 +349,20 @@ module FDRE (
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endcase endgenerate
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endmodule
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(* abc9_box_id=1101, lib_whitebox, abc9_flop *)
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module FDRE_1 (
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(* abc9_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, R
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
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endmodule
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(* abc9_box_id=1102, lib_whitebox, abc9_flop *)
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module FDSE (
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(* abc9_arrival=303 *)
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output reg Q,
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@ -371,6 +386,19 @@ module FDSE (
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endcase endgenerate
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endmodule
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(* abc9_box_id=1103, lib_whitebox, abc9_flop *)
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module FDSE_1 (
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(* abc9_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, S
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
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endmodule
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module FDRSE (
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output reg Q,
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(* clkbuf_sink *)
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@ -406,6 +434,7 @@ module FDRSE (
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Q <= d;
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endmodule
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(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
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module FDCE (
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(* abc9_arrival=303 *)
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output reg Q,
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@ -413,10 +442,10 @@ module FDCE (
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(* invertible_pin = "IS_C_INVERTED" *)
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input C,
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input CE,
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(* invertible_pin = "IS_D_INVERTED" *)
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input D,
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(* invertible_pin = "IS_CLR_INVERTED" *)
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input CLR
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input CLR,
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(* invertible_pin = "IS_D_INVERTED" *)
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input D
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);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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@ -431,6 +460,20 @@ module FDCE (
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endcase endgenerate
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endmodule
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(* abc9_box_id=1105, lib_whitebox, abc9_flop *)
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module FDCE_1 (
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(* abc9_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, CLR
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
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endmodule
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(* abc9_box_id=1106, lib_whitebox, abc9_flop *)
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module FDPE (
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(* abc9_arrival=303 *)
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output reg Q,
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@ -456,6 +499,19 @@ module FDPE (
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endcase endgenerate
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endmodule
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(* abc9_box_id=1107, lib_whitebox, abc9_flop *)
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module FDPE_1 (
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(* abc9_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, PRE
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
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endmodule
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module FDCPE (
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output wire Q,
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(* clkbuf_sink *)
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@ -501,54 +557,6 @@ module FDCPE (
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assign Q = qs ? qp : qc;
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endmodule
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module FDRE_1 (
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(* abc9_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, R
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
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endmodule
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module FDSE_1 (
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(* abc9_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, S
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
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endmodule
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module FDCE_1 (
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(* abc9_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, CLR
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
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endmodule
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module FDPE_1 (
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(* abc9_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, PRE
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
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endmodule
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module LDCE (
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output reg Q,
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(* invertible_pin = "IS_CLR_INVERTED" *)
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@ -1648,7 +1656,7 @@ module SRL16 (
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endmodule
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module SRL16E (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
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(* abc9_arrival=1472 *)
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output Q,
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input A0, A1, A2, A3, CE,
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@ -1712,9 +1720,10 @@ module SRLC16E (
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endmodule
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module SRLC32E (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
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(* abc9_arrival=1472 *)
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output Q,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
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(* abc9_arrival=1114 *)
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output Q31,
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input [4:0] A,
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@ -2356,7 +2365,7 @@ module DSP48E1 (
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parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
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initial begin
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
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if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value");
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if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
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@ -2519,12 +2528,12 @@ module DSP48E1 (
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case (OPMODEr[1:0])
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2'b00: X = 48'b0;
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2'b01: begin X = $signed(Mrx);
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01");
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`endif
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end
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2'b10: begin X = P;
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10");
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`endif
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end
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@ -2536,7 +2545,7 @@ module DSP48E1 (
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case (OPMODEr[3:2])
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2'b00: Y = 48'b0;
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2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling?
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01");
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`endif
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end
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@ -2550,13 +2559,13 @@ module DSP48E1 (
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3'b000: Z = 48'b0;
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3'b001: Z = PCIN;
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3'b010: begin Z = P;
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010");
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`endif
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end
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3'b011: Z = Cr;
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3'b100: begin Z = P;
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`ifdef __ICARUS__
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`ifndef YOSYS
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100");
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if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100");
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`endif
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