mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-15 13:28:59 +00:00
Code Activity

memory_map: Use const drivers instead of FFs for ROMs.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2022-06-17 14:11:04 +02:00
parent bb634d39ef
commit 01daa077a2
1 changed files with 58 additions and 51 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
passes/memory/memory_map.cc
View file

@ -191,6 +191,10 @@ struct MemoryMapWorker
data_reg_out[idx] = static_cells_map[addr]; data_reg_out[idx] = static_cells_map[addr];
count_static++; count_static++;
} }
else if (mem.wr_ports.empty())
{
data_reg_out[idx] = init_data.extract(i*mem.width, mem.width);
}
else else
{ {
RTLIL::Cell *c = module->addCell(genid(mem.memid, "", addr), ID($dff)); RTLIL::Cell *c = module->addCell(genid(mem.memid, "", addr), ID($dff));
@ -266,6 +270,8 @@ struct MemoryMapWorker
log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux);
if (!mem.wr_ports.empty())
{
for (int i = 0; i < mem.size; i++) for (int i = 0; i < mem.size; i++)
{ {
int addr = i + mem.start_offset; int addr = i + mem.start_offset;
@ -330,6 +336,7 @@ struct MemoryMapWorker
module->connect(RTLIL::SigSig(data_reg_in[idx], sig)); module->connect(RTLIL::SigSig(data_reg_in[idx], sig));
} }
}
log(" write interface: %d write mux blocks.\n", count_wrmux); log(" write interface: %d write mux blocks.\n", count_wrmux);