From 01d80c74038dfb727e2ee19af53b813c4de364ef Mon Sep 17 00:00:00 2001
From: clemens <cwalter@ethz.ch>
Date: Sat, 19 Apr 2025 20:41:10 +0200
Subject: [PATCH] add testcase

---
 tests/various/stat.ys | 49 +++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/tests/various/stat.ys b/tests/various/stat.ys
index ad96fe8d4..7c8700494 100644
--- a/tests/various/stat.ys
+++ b/tests/various/stat.ys
@@ -1,4 +1,4 @@
-read_rtlil << EOF
+read_rtlil << EOT
 module \top
   wire input 1 \A
   wire output 2 \Y
@@ -8,7 +8,52 @@ module \top
     connect \Y \Y
   end
 end
-EOF
+EOT
 logger -expect log "Chip area for module '\\top': 9.072000" 1
 logger -expect-no-warnings
 stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
+
+
+design -reset
+read_rtlil <<EOT
+module \top
+  wire input 1 \A
+  wire output 2 \Y
+  wire output 3 \NY
+  cell \child \sequential
+    connect \A \A
+    connect \B 1'0
+    connect \R 1'0
+    connect \Y \Y
+    connect \NY \NY
+  end
+
+  cell \sg13g2_and2_1 \sub
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+end
+
+module \child
+  wire input 1 \A
+  wire input 2 \B
+  wire input 3 \R
+
+  wire output 4 \Y
+  wire output 5 \NY
+  cell \sg13g2_dfrbp_1 
+    connect \CLK \A
+    connect \D \B
+    connect \Q \Y
+    connect \Q_N \NY
+    connect \RESET_B \R
+  end
+
+  
+end
+EOT
+logger -expect log "Chip area for module '\\top': 63.504000" 1
+logger -expect log "of which used for sequential elements: 54.432000 (85.71%) " 1
+logger -expect-no-warnings
+stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz