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Cleanup

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This commit is contained in:
Eddie Hung 2019-09-05 10:07:56 -07:00
parent aa462da395
commit 0166e02e78
1 changed files with 2 additions and 5 deletions
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7
passes/pmgen/xilinx_dsp.pmg
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@ -1,14 +1,14 @@
pattern xilinx_dsp
state <SigBit> clock
state <SigSpec> sigA sigffAmux sigB sigC sigM sigP sigPused
state <SigSpec> sigA sigffAmux sigB sigC sigM sigP
state <IdString> ffAmuxAB ffMmuxAB postAddAB postAddMuxAB
match dsp
select dsp->type.in(\DSP48E1)
endmatch
code sigA sigB
code sigA sigffAmux sigB sigM
sigA = port(dsp, \A);
int i;
for (i = GetSize(sigA)-1; i > 0; i--)
@ -26,12 +26,9 @@ code sigA sigB
if (sigB[i].wire)
++i;
sigB.remove(i, GetSize(sigB)-i);
endcode
code sigM
SigSpec P = port(dsp, \P);
// Only care about those bits that are used
int i;
for (i = 0; i < GetSize(P); i++) {
if (nusers(P[i]) <= 1)
break;