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Merge pull request #3014 from YosysHQ/claire/fix-vgtest

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Fix "make vgtest"
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Claire Xen 2021-09-24 17:50:34 +02:00 • committed by GitHub
commit 0146d83ed8
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41 changed files with 80 additions and 79 deletions
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frontends/verilog/verilog_parser.y
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@ -2677,6 +2677,7 @@ for_initialization:
AstNode *node = new AstNode(AST_ASSIGN_EQ, ident, $3);
ast_stack.back()->children.push_back(node);
SET_AST_NODE_LOC(node, @1, @3);
delete $1;
} |
non_io_wire_type range TOK_ID {
frontend_verilog_yyerror("For loop variable declaration is missing initialization!");