mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 01:55:33 +00:00
Code Activity

Fix issue with part of PI being 1'bx

Browse source
This commit is contained in:
Eddie Hung 2019-06-20 17:29:45 -07:00
parent f11c9a419b
commit 014606affe
2 changed files with 11 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

10
frontends/aiger/aigerparse.cc
View file

@ -947,11 +947,13 @@ void AigerReader::post_process()
if (other_wire) {
other_wire->port_input = false;
other_wire->port_output = false;
if (wire->port_input)
module->connect(other_wire, SigSpec(wire, i));
else
module->connect(SigSpec(wire, i), other_wire);
}
if (wire->port_input && other_wire)
module->connect(other_wire, SigSpec(wire, i));
else
// Since we skip POs that are connected to Sx,
// re-connect them here
module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
}
}