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memory blocks

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Miodrag Milanovic 2024-03-13 09:26:19 +01:00
parent 3ed5ea24b2
commit 012f0e2952
7 changed files with 1278 additions and 384 deletions
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384
techlibs/nanoxplore/cells_bb.v
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@ -3324,349 +3324,6 @@ module NX_RB_WRAP(EI_CK, EO_CK, CK, EO, EI, FI, FO);
parameter outputContext = "";
endmodule
(* blackbox *)
module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
output COR;
output ERR;
input I1;
input I10;
input I11;
input I12;
input I13;
input I14;
input I15;
input I16;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
input I8;
input I9;
output O1;
output O10;
output O11;
output O12;
output O13;
output O14;
output O15;
output O16;
output O2;
output O3;
output O4;
output O5;
output O6;
output O7;
output O8;
output O9;
input RA1;
input RA2;
input RA3;
input RA4;
input RA5;
input RA6;
input RCK;
input RE;
input WA1;
input WA2;
input WA3;
input WA4;
input WA5;
input WA6;
input WCK;
input WE;
parameter addr_mask = 5'b00000;
parameter mem_ctxt = "";
parameter rck_edge = 1'b0;
parameter wck_edge = 1'b0;
parameter we_mask = 1'b0;
parameter wea_mask = 1'b0;
endmodule
(* blackbox *)
module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA);
input [17:0] I;
output [17:0] O;
input [4:0] RA;
input [4:0] WA;
input WCK;
input WE;
input WEA;
parameter mem_ctxt = "";
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA);
input [17:0] I;
output [17:0] O;
input [4:0] WA;
input WCK;
input WE;
input WEA;
parameter mem_ctxt = "";
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
output COR;
output ERR;
input I1;
input I10;
input I11;
input I12;
input I13;
input I14;
input I15;
input I16;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
input I8;
input I9;
output O1;
output O10;
output O11;
output O12;
output O13;
output O14;
output O15;
output O16;
output O2;
output O3;
output O4;
output O5;
output O6;
output O7;
output O8;
output O9;
input RA1;
input RA2;
input RA3;
input RA4;
input RA5;
input RA6;
input RCK;
input RE;
input WA1;
input WA2;
input WA3;
input WA4;
input WA5;
input WA6;
input WCK;
input WE;
parameter mem_ctxt = "";
parameter mode = 0;
parameter rck_edge = 1'b0;
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_RFB_L_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);
output COR;
output ERR;
input [15:0] I;
output [15:0] O;
input [5:0] RA;
input RCK;
input RE;
input [5:0] WA;
input WCK;
input WE;
parameter mem_ctxt = "";
parameter mode = 0;
parameter rck_edge = 1'b0;
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
output COR;
output ERR;
input I1;
input I10;
input I11;
input I12;
input I13;
input I14;
input I15;
input I16;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
input I8;
input I9;
output O1;
output O10;
output O11;
output O12;
output O13;
output O14;
output O15;
output O16;
output O2;
output O3;
output O4;
output O5;
output O6;
output O7;
output O8;
output O9;
input RA1;
input RA2;
input RA3;
input RA4;
input RA5;
input RA6;
input RCK;
input RE;
input WA1;
input WA2;
input WA3;
input WA4;
input WA5;
input WA6;
input WCK;
input WE;
parameter mem_ctxt = "";
parameter rck_edge = 1'b0;
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1
, WA2, WA3, WA4, WA5, WA6, WE, WEA);
input I1;
input I10;
input I11;
input I12;
input I13;
input I14;
input I15;
input I16;
input I17;
input I18;
input I19;
input I2;
input I20;
input I21;
input I22;
input I23;
input I24;
input I25;
input I26;
input I27;
input I28;
input I29;
input I3;
input I30;
input I31;
input I32;
input I33;
input I34;
input I35;
input I36;
input I4;
input I5;
input I6;
input I7;
input I8;
input I9;
output O1;
output O10;
output O11;
output O12;
output O13;
output O14;
output O15;
output O16;
output O17;
output O18;
output O19;
output O2;
output O20;
output O21;
output O22;
output O23;
output O24;
output O25;
output O26;
output O27;
output O28;
output O29;
output O3;
output O30;
output O31;
output O32;
output O33;
output O34;
output O35;
output O36;
output O4;
output O5;
output O6;
output O7;
output O8;
output O9;
input RA1;
input RA10;
input RA2;
input RA3;
input RA4;
input RA5;
input RA6;
input RA7;
input RA8;
input RA9;
input WA1;
input WA2;
input WA3;
input WA4;
input WA5;
input WA6;
input WCK;
input WE;
input WEA;
parameter mem_ctxt = "";
parameter mode = 0;
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_RFB_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);
output COR;
output ERR;
input [15:0] I;
output [15:0] O;
input [5:0] RA;
input RCK;
input RE;
input [5:0] WA;
input WCK;
input WE;
parameter mem_ctxt = "";
parameter rck_edge = 1'b0;
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
input DCK;
@ -3784,47 +3441,6 @@ module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO,
parameter wck_edge = 1'b0;
endmodule
(* blackbox *)
module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA);
output [17:0] AO;
input [4:0] ARA;
output [17:0] BO;
input [4:0] BRA;
input [17:0] I;
input [4:0] WA;
input WCK;
input WE;
input WEA;
parameter mem_ctxt = "";
parameter wck_edge = 1'b0;
endmodule
//(* blackbox *)
//module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA);
// input [35:0] I;
// output [35:0] O;
// input [4:0] RA;
// input [4:0] WA;
// input WCK;
// input WE;
// input WEA;
// parameter mem_ctxt = "";
// parameter wck_edge = 1'b0;
//endmodule
//
//(* blackbox *)
//module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA);
// input [17:0] I;
// output [17:0] O;
// input [5:0] RA;
// input [5:0] WA;
// input WCK;
// input WE;
// input WEA;
// parameter mem_ctxt = "";
// parameter wck_edge = 1'b0;
//endmodule
(* blackbox *)
module SMACC24x18_1DSP(clk, rst, A, B, Z);
input [23:0] A;