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Add tests for these new models

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Eddie Hung 2019-12-12 18:52:48 -08:00
parent 8925bf4b96
commit 01116f0f0a
1 changed files with 40 additions and 0 deletions
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tests/arch/xilinx/lutram.ys
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@ -97,3 +97,43 @@ select -assert-count 1 t:BUFG
select -assert-count 24 t:FDRE select -assert-count 24 t:FDRE
select -assert-count 8 t:RAM64M select -assert-count 8 t:RAM64M
select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 1 t:RAM32M
select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D
design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 2 t:RAM64M
select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D