mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-22 20:32:07 +00:00
Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
This commit is contained in:
parent
4f2b78e19a
commit
00e7dec7f5
28 changed files with 206 additions and 178 deletions
|
@ -985,7 +985,7 @@ struct TechmapPass : public Pass {
|
|||
log(" techmap [-map filename] [selection]\n");
|
||||
log("\n");
|
||||
log("This pass implements a very simple technology mapper that replaces cells in\n");
|
||||
log("the design with implementations given in form of a Verilog or ilang source\n");
|
||||
log("the design with implementations given in form of a Verilog or RTLIL source\n");
|
||||
log("file.\n");
|
||||
log("\n");
|
||||
log(" -map filename\n");
|
||||
|
@ -1212,7 +1212,7 @@ struct TechmapPass : public Pass {
|
|||
if (!map->module(mod->name))
|
||||
map->add(mod->clone());
|
||||
} else {
|
||||
Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
|
||||
Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue