mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 14:13:23 +00:00
Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
This commit is contained in:
whitequark
parent
4f2b78e19a
commit
00e7dec7f5
28 changed files with 206 additions and 178 deletions
536
backends/rtlil/rtlil_backend.cc
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536
backends/rtlil/rtlil_backend.cc
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* A very simple and straightforward backend for the RTLIL text
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* representation.
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*
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*/
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#include "rtlil_backend.h"
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#include "kernel/yosys.h"
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#include <errno.h>
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USING_YOSYS_NAMESPACE
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using namespace RTLIL_BACKEND;
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YOSYS_NAMESPACE_BEGIN
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void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint)
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{
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if (width < 0)
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width = data.bits.size() - offset;
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if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
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if (width == 32 && autoint) {
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int32_t val = 0;
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for (int i = 0; i < width; i++) {
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log_assert(offset+i < (int)data.bits.size());
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switch (data.bits[offset+i]) {
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case State::S0: break;
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case State::S1: val |= 1 << i; break;
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default: val = -1; break;
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}
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}
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if (val >= 0) {
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f << stringf("%d", val);
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return;
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}
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}
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f << stringf("%d'", width);
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for (int i = offset+width-1; i >= offset; i--) {
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log_assert(i < (int)data.bits.size());
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switch (data.bits[i]) {
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case State::S0: f << stringf("0"); break;
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case State::S1: f << stringf("1"); break;
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case RTLIL::Sx: f << stringf("x"); break;
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case RTLIL::Sz: f << stringf("z"); break;
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case RTLIL::Sa: f << stringf("-"); break;
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case RTLIL::Sm: f << stringf("m"); break;
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}
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}
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} else {
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f << stringf("\"");
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std::string str = data.decode_string();
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for (size_t i = 0; i < str.size(); i++) {
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if (str[i] == '\n')
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f << stringf("\\n");
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else if (str[i] == '\t')
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f << stringf("\\t");
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else if (str[i] < 32)
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f << stringf("\\%03o", str[i]);
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else if (str[i] == '"')
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f << stringf("\\\"");
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else if (str[i] == '\\')
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f << stringf("\\\\");
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else
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f << str[i];
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}
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f << stringf("\"");
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}
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}
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void RTLIL_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint)
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{
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if (chunk.wire == NULL) {
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dump_const(f, chunk.data, chunk.width, chunk.offset, autoint);
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} else {
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if (chunk.width == chunk.wire->width && chunk.offset == 0)
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f << stringf("%s", chunk.wire->name.c_str());
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else if (chunk.width == 1)
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f << stringf("%s [%d]", chunk.wire->name.c_str(), chunk.offset);
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else
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f << stringf("%s [%d:%d]", chunk.wire->name.c_str(), chunk.offset+chunk.width-1, chunk.offset);
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}
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}
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void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint)
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{
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if (sig.is_chunk()) {
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dump_sigchunk(f, sig.as_chunk(), autoint);
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} else {
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f << stringf("{ ");
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for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
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dump_sigchunk(f, *it, false);
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f << stringf(" ");
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}
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f << stringf("}");
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}
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}
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void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire)
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{
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for (auto &it : wire->attributes) {
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f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
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dump_const(f, it.second);
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f << stringf("\n");
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}
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f << stringf("%s" "wire ", indent.c_str());
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if (wire->width != 1)
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f << stringf("width %d ", wire->width);
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if (wire->upto)
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f << stringf("upto ");
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if (wire->start_offset != 0)
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f << stringf("offset %d ", wire->start_offset);
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if (wire->port_input && !wire->port_output)
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f << stringf("input %d ", wire->port_id);
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if (!wire->port_input && wire->port_output)
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f << stringf("output %d ", wire->port_id);
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if (wire->port_input && wire->port_output)
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f << stringf("inout %d ", wire->port_id);
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if (wire->is_signed)
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f << stringf("signed ");
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f << stringf("%s\n", wire->name.c_str());
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}
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void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory)
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{
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for (auto &it : memory->attributes) {
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f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
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dump_const(f, it.second);
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f << stringf("\n");
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}
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f << stringf("%s" "memory ", indent.c_str());
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if (memory->width != 1)
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f << stringf("width %d ", memory->width);
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if (memory->size != 0)
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f << stringf("size %d ", memory->size);
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if (memory->start_offset != 0)
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f << stringf("offset %d ", memory->start_offset);
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f << stringf("%s\n", memory->name.c_str());
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}
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void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell)
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{
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for (auto &it : cell->attributes) {
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f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
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dump_const(f, it.second);
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f << stringf("\n");
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}
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f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str());
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for (auto &it : cell->parameters) {
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f << stringf("%s parameter%s%s %s ", indent.c_str(),
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(it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "",
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(it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "",
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it.first.c_str());
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dump_const(f, it.second);
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f << stringf("\n");
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}
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for (auto &it : cell->connections()) {
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f << stringf("%s connect %s ", indent.c_str(), it.first.c_str());
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dump_sigspec(f, it.second);
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f << stringf("\n");
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}
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f << stringf("%s" "end\n", indent.c_str());
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}
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void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs)
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{
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for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it)
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{
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, it->first);
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f << stringf(" ");
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dump_sigspec(f, it->second);
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f << stringf("\n");
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}
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for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it)
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dump_proc_switch(f, indent, *it);
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}
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void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw)
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{
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for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) {
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f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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f << stringf("\n");
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}
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f << stringf("%s" "switch ", indent.c_str());
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dump_sigspec(f, sw->signal);
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f << stringf("\n");
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for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it)
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{
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for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) {
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f << stringf("%s attribute %s ", indent.c_str(), ait->first.c_str());
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dump_const(f, ait->second);
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f << stringf("\n");
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}
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f << stringf("%s case ", indent.c_str());
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for (size_t i = 0; i < (*it)->compare.size(); i++) {
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if (i > 0)
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f << stringf(" , ");
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dump_sigspec(f, (*it)->compare[i]);
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}
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f << stringf("\n");
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dump_proc_case_body(f, indent + " ", *it);
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}
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f << stringf("%s" "end\n", indent.c_str());
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}
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void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy)
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{
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f << stringf("%s" "sync ", indent.c_str());
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switch (sy->type) {
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case RTLIL::ST0: f << stringf("low ");
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if (0) case RTLIL::ST1: f << stringf("high ");
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if (0) case RTLIL::STp: f << stringf("posedge ");
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if (0) case RTLIL::STn: f << stringf("negedge ");
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if (0) case RTLIL::STe: f << stringf("edge ");
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dump_sigspec(f, sy->signal);
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f << stringf("\n");
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break;
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case RTLIL::STa: f << stringf("always\n"); break;
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case RTLIL::STg: f << stringf("global\n"); break;
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case RTLIL::STi: f << stringf("init\n"); break;
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}
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for (auto it = sy->actions.begin(); it != sy->actions.end(); ++it) {
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f << stringf("%s update ", indent.c_str());
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dump_sigspec(f, it->first);
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f << stringf(" ");
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dump_sigspec(f, it->second);
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f << stringf("\n");
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}
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}
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void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc)
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{
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for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) {
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f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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f << stringf("\n");
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}
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f << stringf("%s" "process %s\n", indent.c_str(), proc->name.c_str());
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dump_proc_case_body(f, indent + " ", &proc->root_case);
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for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it)
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dump_proc_sync(f, indent + " ", *it);
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f << stringf("%s" "end\n", indent.c_str());
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}
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void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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{
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f << stringf("%s" "connect ", indent.c_str());
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dump_sigspec(f, left);
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f << stringf(" ");
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dump_sigspec(f, right);
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f << stringf("\n");
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}
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void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
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{
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bool print_header = flag_m || design->selected_whole_module(module->name);
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bool print_body = !flag_n || !design->selected_whole_module(module->name);
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if (print_header)
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{
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for (auto it = module->attributes.begin(); it != module->attributes.end(); ++it) {
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f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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f << stringf("\n");
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}
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f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str());
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if (!module->avail_parameters.empty()) {
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if (only_selected)
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f << stringf("\n");
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for (const auto &p : module->avail_parameters) {
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const auto &it = module->parameter_default_values.find(p);
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if (it == module->parameter_default_values.end()) {
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f << stringf("%s" " parameter %s\n", indent.c_str(), p.c_str());
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} else {
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f << stringf("%s" " parameter %s ", indent.c_str(), p.c_str());
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dump_const(f, it->second);
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f << stringf("\n");
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}
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}
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}
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}
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if (print_body)
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{
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for (auto it : module->wires())
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if (!only_selected || design->selected(module, it)) {
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if (only_selected)
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f << stringf("\n");
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dump_wire(f, indent + " ", it);
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}
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for (auto it : module->memories)
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if (!only_selected || design->selected(module, it.second)) {
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if (only_selected)
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f << stringf("\n");
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dump_memory(f, indent + " ", it.second);
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}
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for (auto it : module->cells())
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if (!only_selected || design->selected(module, it)) {
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if (only_selected)
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f << stringf("\n");
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dump_cell(f, indent + " ", it);
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}
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for (auto it : module->processes)
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if (!only_selected || design->selected(module, it.second)) {
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if (only_selected)
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f << stringf("\n");
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dump_proc(f, indent + " ", it.second);
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}
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bool first_conn_line = true;
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for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
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bool show_conn = !only_selected;
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if (only_selected) {
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RTLIL::SigSpec sigs = it->first;
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sigs.append(it->second);
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for (auto &c : sigs.chunks()) {
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if (c.wire == NULL || !design->selected(module, c.wire))
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continue;
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show_conn = true;
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}
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}
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if (show_conn) {
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if (only_selected && first_conn_line)
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f << stringf("\n");
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dump_conn(f, indent + " ", it->first, it->second);
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first_conn_line = false;
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}
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}
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}
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if (print_header)
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f << stringf("%s" "end\n", indent.c_str());
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}
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void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
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{
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int init_autoidx = autoidx;
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if (!flag_m) {
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int count_selected_mods = 0;
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for (auto module : design->modules()) {
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if (design->selected_whole_module(module->name))
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flag_m = true;
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if (design->selected(module))
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count_selected_mods++;
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}
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if (count_selected_mods > 1)
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flag_m = true;
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}
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if (!only_selected || flag_m) {
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if (only_selected)
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f << stringf("\n");
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f << stringf("autoidx %d\n", autoidx);
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}
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for (auto module : design->modules()) {
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if (!only_selected || design->selected(module)) {
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if (only_selected)
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f << stringf("\n");
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dump_module(f, "", module, design, only_selected, flag_m, flag_n);
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}
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}
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log_assert(init_autoidx == autoidx);
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}
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YOSYS_NAMESPACE_END
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PRIVATE_NAMESPACE_BEGIN
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struct RTLILBackend : public Backend {
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RTLILBackend() : Backend("rtlil", "write design to RTLIL file") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" write_rtlil [filename]\n");
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log("\n");
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log("Write the current design to an RTLIL file. (RTLIL is a text representation\n");
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log("of a design in yosys's internal format.)\n");
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log("\n");
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log(" -selected\n");
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log(" only write selected parts of the design.\n");
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log("\n");
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool selected = false;
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log_header(design, "Executing RTLIL backend.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
std::string arg = args[argidx];
|
||||
if (arg == "-selected") {
|
||||
selected = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(f, filename, args, argidx);
|
||||
|
||||
design->sort();
|
||||
|
||||
log("Output filename: %s\n", filename.c_str());
|
||||
*f << stringf("# Generated by %s\n", yosys_version_str);
|
||||
RTLIL_BACKEND::dump_design(*f, design, selected, true, false);
|
||||
}
|
||||
} RTLILBackend;
|
||||
|
||||
struct IlangBackend : public Backend {
|
||||
IlangBackend() : Backend("ilang", "(deprecated) alias of write_rtlil") { }
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log("See `help write_rtlil`.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
RTLILBackend.execute(f, filename, args, design);
|
||||
}
|
||||
} IlangBackend;
|
||||
|
||||
struct DumpPass : public Pass {
|
||||
DumpPass() : Pass("dump", "print parts of the design in RTLIL format") { }
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" dump [options] [selection]\n");
|
||||
log("\n");
|
||||
log("Write the selected parts of the design to the console or specified file in\n");
|
||||
log("RTLIL format.\n");
|
||||
log("\n");
|
||||
log(" -m\n");
|
||||
log(" also dump the module headers, even if only parts of a single\n");
|
||||
log(" module is selected\n");
|
||||
log("\n");
|
||||
log(" -n\n");
|
||||
log(" only dump the module headers if the entire module is selected\n");
|
||||
log("\n");
|
||||
log(" -o <filename>\n");
|
||||
log(" write to the specified file.\n");
|
||||
log("\n");
|
||||
log(" -a <filename>\n");
|
||||
log(" like -outfile but append instead of overwrite\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
std::string filename;
|
||||
bool flag_m = false, flag_n = false, append = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
std::string arg = args[argidx];
|
||||
if ((arg == "-o" || arg == "-outfile") && argidx+1 < args.size()) {
|
||||
filename = args[++argidx];
|
||||
append = false;
|
||||
continue;
|
||||
}
|
||||
if ((arg == "-a" || arg == "-append") && argidx+1 < args.size()) {
|
||||
filename = args[++argidx];
|
||||
append = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-m") {
|
||||
flag_m = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-n") {
|
||||
flag_n = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
std::ostream *f;
|
||||
std::stringstream buf;
|
||||
|
||||
if (!filename.empty()) {
|
||||
rewrite_filename(filename);
|
||||
std::ofstream *ff = new std::ofstream;
|
||||
ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc);
|
||||
if (ff->fail()) {
|
||||
delete ff;
|
||||
log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
|
||||
}
|
||||
f = ff;
|
||||
} else {
|
||||
f = &buf;
|
||||
}
|
||||
|
||||
RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n);
|
||||
|
||||
if (!filename.empty()) {
|
||||
delete f;
|
||||
} else {
|
||||
log("%s", buf.str().c_str());
|
||||
}
|
||||
}
|
||||
} DumpPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
Loading…
Add table
Add a link
Reference in a new issue