mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	intel_alm: re-enable carry chains for ABC9
This commit is contained in:
		
							parent
							
								
									52c8c28d2c
								
							
						
					
					
						commit
						00b0e850db
					
				
					 2 changed files with 5 additions and 7 deletions
				
			
		|  | @ -283,10 +283,8 @@ assign Q = ~A; | ||||||
| 
 | 
 | ||||||
| endmodule | endmodule | ||||||
| 
 | 
 | ||||||
| // Despite the abc9_carry attributes, this doesn't seem to stop ABC9 adding illegal fanout to the carry chain that nextpnr cannot handle.
 | (* abc9_box, lib_whitebox *) | ||||||
| // So we treat it as a total blackbox from ABC9's perspective for now.
 | module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO); | ||||||
| // (* abc9_box, lib_whitebox *)
 |  | ||||||
| module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, /* (* abc9_carry *) */ input CI, output SO, /* (* abc9_carry *) */ output CO); |  | ||||||
| 
 | 
 | ||||||
| parameter LUT0 = 16'h0000; | parameter LUT0 = 16'h0000; | ||||||
| parameter LUT1 = 16'h0000; | parameter LUT1 = 16'h0000; | ||||||
|  |  | ||||||
|  | @ -6,7 +6,7 @@ equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm | ||||||
| design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) | design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) | ||||||
| cd top # Constrain all select calls below inside the top module | cd top # Constrain all select calls below inside the top module | ||||||
| 
 | 
 | ||||||
| select -assert-count 1 t:MISTRAL_NOT | select -assert-count 2 t:MISTRAL_NOT | ||||||
| select -assert-count 8 t:MISTRAL_ALUT_ARITH | select -assert-count 8 t:MISTRAL_ALUT_ARITH | ||||||
| select -assert-count 8 t:MISTRAL_FF | select -assert-count 8 t:MISTRAL_FF | ||||||
| select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D | select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D | ||||||
|  | @ -21,7 +21,7 @@ equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm | ||||||
| design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) | design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) | ||||||
| cd top # Constrain all select calls below inside the top module | cd top # Constrain all select calls below inside the top module | ||||||
| 
 | 
 | ||||||
| select -assert-count 1 t:MISTRAL_NOT | select -assert-count 2 t:MISTRAL_NOT | ||||||
| select -assert-count 8 t:MISTRAL_ALUT_ARITH | select -assert-count 8 t:MISTRAL_ALUT_ARITH | ||||||
| select -assert-count 8 t:MISTRAL_FF | select -assert-count 8 t:MISTRAL_FF | ||||||
| select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D | select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D | ||||||
|  |  | ||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue