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Major redesign of expr width/sign detecion (verilog/ast frontend)

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This commit is contained in:
Clifford Wolf 2013-07-09 14:31:57 +02:00
parent e8da3ea7b6
commit 00a6c1d9a5
5 changed files with 189 additions and 37 deletions
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4
tests/tools/autotest.sh
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@ -51,7 +51,7 @@ create_ref() {
(
set +x
prefix="$2"
xilver=$( ls -v /opt/Xilinx/ | tail -n1; )
xilver=$( ls -v /opt/Xilinx/ | grep '^[0-9]' | tail -n1; )
case "$( uname -m )" in
x86_64)
set --; . /opt/Xilinx/$xilver/ISE_DS/settings64.sh ;;
@ -73,7 +73,7 @@ compile_and_run() {
(
set +x
files=( "$@" )
xilver=$( ls -v /opt/Xilinx/ | tail -n1; )
xilver=$( ls -v /opt/Xilinx/ | grep '^[0-9]' | tail -n1; )
case "$( uname -m )" in
x86_64)
set --; . /opt/Xilinx/$xilver/ISE_DS/settings64.sh ;;