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Major redesign of expr width/sign detecion (verilog/ast frontend)

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This commit is contained in:
Clifford Wolf 2013-07-09 14:31:57 +02:00
parent e8da3ea7b6
commit 00a6c1d9a5
5 changed files with 189 additions and 37 deletions
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18
tests/simple/signedexpr.v Normal file
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module test01(a, b, xu, xs, yu, ys, zu, zs);
input signed [1:0] a;
input signed [2:0] b;
output [3:0] xu, xs;
output [3:0] yu, ys;
output zu, zs;
assign xu = (a + b) + 3'd0;
assign xs = (a + b) + 3'sd0;
assign yu = {a + b} + 3'd0;
assign ys = {a + b} + 3'sd0;
assign zu = a + b != 3'd0;
assign zs = a + b != 3'sd0;
endmodule