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Major redesign of expr width/sign detecion (verilog/ast frontend)

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This commit is contained in:
Clifford Wolf 2013-07-09 14:31:57 +02:00
parent e8da3ea7b6
commit 00a6c1d9a5
5 changed files with 189 additions and 37 deletions
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2
frontends/verilog/const2ast.cc
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@ -161,7 +161,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
if (str == endptr)
intval = -1;
// The "<bits>'[bodh]<digits>" syntax
// The "<bits>'s?[bodh]<digits>" syntax
if (*endptr == '\'')
{
int len_in_bits = intval;