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rtlil: Make Process handling more uniform with Cell and Wire.

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- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
This commit is contained in:
Marcelina Kościelnicka 2021-07-11 23:57:53 +02:00
parent 726fabd65e
commit 009940f56c
8 changed files with 62 additions and 25 deletions
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10
passes/cmds/delete.cc
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@ -90,7 +90,7 @@ struct DeletePass : public Pass {
pool<RTLIL::Wire*> delete_wires;
pool<RTLIL::Cell*> delete_cells;
pool<RTLIL::IdString> delete_procs;
pool<RTLIL::Process*> delete_procs;
pool<RTLIL::IdString> delete_mems;
for (auto wire : module->selected_wires())
@ -110,7 +110,7 @@ struct DeletePass : public Pass {
for (auto &it : module->processes)
if (design->selected(module, it.second))
delete_procs.insert(it.first);
delete_procs.insert(it.second);
for (auto &it : delete_mems) {
delete module->memories.at(it);
@ -120,10 +120,8 @@ struct DeletePass : public Pass {
for (auto &it : delete_cells)
module->remove(it);
for (auto &it : delete_procs) {
delete module->processes.at(it);
module->processes.erase(it);
}
for (auto &it : delete_procs)
module->remove(it);
module->remove(delete_wires);