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rtlil: Make Process handling more uniform with Cell and Wire.

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- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
This commit is contained in:
Marcelina Kościelnicka 2021-07-11 23:57:53 +02:00
parent 726fabd65e
commit 009940f56c
8 changed files with 62 additions and 25 deletions
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9
passes/cmds/bugpoint.cc
View file

@ -275,7 +275,7 @@ struct BugpointPass : public Pass {
if (mod->get_blackbox_attribute())
continue;
RTLIL::IdString removed_process;
RTLIL::Process *removed_process = nullptr;
for (auto process : mod->processes)
{
if (process.second->get_bool_attribute(ID::bugpoint_keep))
@ -284,13 +284,12 @@ struct BugpointPass : public Pass {
if (index++ == seed)
{
log_header(design, "Trying to remove process %s.%s.\n", log_id(mod), log_id(process.first));
removed_process = process.first;
removed_process = process.second;
break;
}
}
if (!removed_process.empty()) {
delete mod->processes[removed_process];
mod->processes.erase(removed_process);
if (removed_process) {
mod->remove(removed_process);
return design_copy;
}
}

10
passes/cmds/delete.cc
View file

@ -90,7 +90,7 @@ struct DeletePass : public Pass {
pool<RTLIL::Wire*> delete_wires;
pool<RTLIL::Cell*> delete_cells;
pool<RTLIL::IdString> delete_procs;
pool<RTLIL::Process*> delete_procs;
pool<RTLIL::IdString> delete_mems;
for (auto wire : module->selected_wires())
@ -110,7 +110,7 @@ struct DeletePass : public Pass {
for (auto &it : module->processes)
if (design->selected(module, it.second))
delete_procs.insert(it.first);
delete_procs.insert(it.second);
for (auto &it : delete_mems) {
delete module->memories.at(it);
@ -120,10 +120,8 @@ struct DeletePass : public Pass {
for (auto &it : delete_cells)
module->remove(it);
for (auto &it : delete_procs) {
delete module->processes.at(it);
module->processes.erase(it);
}
for (auto &it : delete_procs)
module->remove(it);
module->remove(delete_wires);

9
passes/proc/proc_clean.cc
View file

@ -209,7 +209,7 @@ struct ProcCleanPass : public Pass {
extra_args(args, argidx, design);
for (auto mod : design->modules()) {
std::vector<RTLIL::IdString> delme;
std::vector<RTLIL::Process *> delme;
if (!design->selected(mod))
continue;
for (auto &proc_it : mod->processes) {
@ -220,12 +220,11 @@ struct ProcCleanPass : public Pass {
proc_it.second->root_case.actions.size() == 0) {
if (!quiet)
log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
delme.push_back(proc_it.first);
delme.push_back(proc_it.second);
}
}
for (auto &id : delme) {
delete mod->processes[id];
mod->processes.erase(id);
for (auto proc : delme) {
mod->remove(proc);
}
}