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rtlil: Make Process handling more uniform with Cell and Wire.

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- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
This commit is contained in:
Marcelina Kościelnicka 2021-07-11 23:57:53 +02:00
parent 726fabd65e
commit 009940f56c
8 changed files with 62 additions and 25 deletions
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4
frontends/ast/genrtlil.cc
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@ -319,16 +319,14 @@ struct AST_INTERNAL::ProcessGenerator
LookaheadRewriter la_rewriter(always);
// generate process and simple root case
proc = new RTLIL::Process;
proc = current_module->addProcess(stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++));
set_src_attr(proc, always);
proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT)
log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n",
attr.first.c_str());
proc->attributes[attr.first] = attr.second->asAttrConst();
}
current_module->processes[proc->name] = proc;
current_case = &proc->root_case;
// create initial temporary signal for all output registers