mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-16 07:45:28 +00:00
Code Activity

sv: fix support wire and var data type modifiers

Browse source
This commit is contained in:
Zachary Snow 2021-01-20 09:15:48 -07:00
parent 4762cc06c6
commit 006c18fc11
3 changed files with 65 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

9
tests/verilog/wire_and_var.ys Normal file
View file

@ -0,0 +1,9 @@
logger -expect warning "wire '\\wire_1' is assigned in a block" 1
logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1
logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1
logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1
logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1
read_verilog -sv wire_and_var.sv