read_verilog spram.v
hierarchy -top top
synth_ice40
select -assert-count 1 t:SB_SPRAM256KA
select -assert-none t:SB_SPRAM256KA %% t:* %D

# Testing with pattern as described in pattern document
design -reset
read_verilog spram.v
chparam -set SKIP_RDEN 0
hierarchy -top top
synth_ice40
select -assert-count 1 t:SB_SPRAM256KA
# Below fails due to extra SB_LUT4
# select -assert-none t:SB_SPRAM256KA %% t:* %D
