read_verilog -sv <<EOF
typedef logic T;
typedef T [3:0] S;
EOF

read_verilog -sv <<EOF
module example;
    // S and T refer to the definitions from the first file
    T t;
    S s;
    always @* begin
        assert ($bits(t) == 1);
        assert ($bits(s) == 4);
    end
endmodule

typedef byte T;
typedef T S;

module top;
    // S and T refer to the most recent overrides
    T t;
    S s;
    always @* begin
        assert ($bits(t) == 8);
        assert ($bits(s) == 8);
    end
    example e();
endmodule
EOF

hierarchy
proc
flatten
opt -full
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
