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	title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic},
	author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm},
	booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages},
	pages={194--201},
	year={2012}
}

@incollection{intersynthFdlBookChapter,
	title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures},
	author={Johann Glaser and Clifford Wolf},
	booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12},
	editor={Jan Haase},
	publisher={Springer},
	year={2013},
	note={to appear}
}

@unpublished{BACC,
	author = {Clifford Wolf},
	title = {Design and Implementation of the Yosys Open SYnthesis Suite},
	note = {Bachelor Thesis, Vienna University of Technology},
	year = {2013}
}

@unpublished{VerilogFossEval,
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	year = {2012}
}

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@MISC{Odin,
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@inproceedings{vtr2012,
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  pages={77--86},
  year={2012},
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}

@MISC{LogicSynthesis,
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@ARTICLE{Verilog2005, 
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@ARTICLE{VerilogSynth, 
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	year={2002}, 
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@ARTICLE{VHDL,
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@ARTICLE{VHDLSynth,
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@ARTICLE{IP-XACT, 
journal={IEEE Std 1685-2009}, title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, 
year={2010}, 
pages={C1-360}, 
keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, 
doi={10.1109/IEEESTD.2010.5417309},}

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@INPROCEEDINGS{Cummings00,
author = {Clifford E. Cummings and Sunburst Design Inc},
title = {Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill},
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@ARTICLE{MURPHY,
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@INPROCEEDINGS{fsmextract, 
author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, 
booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, 
title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, 
year={2010}, 
pages={2610-2613}, 
keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, 
doi={10.1109/ISCAS.2010.5537093},}

@ARTICLE{MultiLevelLogicSynth, 
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year={1990}, 
volume={78}, 
number={2}, 
pages={264-300}, 
keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, 
doi={10.1109/5.52213}, 
ISSN={0018-9219},}

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	publisher = {ACM},
	address = {New York, NY, USA},
} 
