# read design
read_verilog counter.v
hierarchy -check -top counter

# the high-level stuff
proc; opt; memory; opt; fsm; opt

# mapping to internal cell library
techmap; opt

# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib

# mapping logic to mycells.lib
abc -liberty mycells.lib

# cleanup
clean

# write synthesized design
write_verilog synth.v
