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Jannis Harder fedfae0e9c examples: Fix use of SVA value change expressions
The $stable value change expression cannot be true for a non-x signal in
the initial state. This is now correctly handled by the verific import,
so the dpmem example needs to start assuming `$stable` only after
leaving the initial state.
2022-05-11 10:38:54 +02:00
.github/workflows fix ci 2022-03-07 08:34:01 +01:00
docs examples: Fix use of SVA value change expressions 2022-05-11 10:38:54 +02:00
extern Fixed names and links 2021-10-31 14:42:39 +01:00
sbysrc Add --dumptaskinfo option to output some .sby metadata as json 2022-04-11 17:44:10 +02:00
tests Refactor tests 2022-04-11 17:50:38 +02:00
.gitignore Add aiger engine 2017-02-19 23:53:01 +01:00
.readthedocs.yaml update docs theme 2021-11-26 20:34:55 +01:00
COPYING Fixed names and links 2021-10-31 14:42:39 +01:00
Makefile sed -i option is not posix, and argument syntax is incompatible between mac and linux. use redirects instead 2020-10-09 12:04:19 +02:00
README.md mention tabby+oss cad suite in readme 2022-01-04 16:32:59 +01:00

SymbiYosys (sby) is a front-end driver program for Yosys-based formal hardware verification flows. See https://yosyshq.readthedocs.io/projects/sby/ for documentation on how to use SymbiYosys.

SymbiYosys (sby) itself is licensed under the ISC license, note that the solvers and other components used by SymbiYosys come with their own license terms. There is some more details in the "Selecting the right engine" section of the documentation.


SymbiYosys (sby) is part of the Tabby CAD Suite and the OSS CAD Suite! The easiest way to use sby is to install the binary software suite, which contains all required dependencies, including all supported solvers.

Make sure to get a Tabby CAD Suite Evaluation License for extensive SystemVerilog Assertion (SVA) support, as well as industry-grade SystemVerilog and VHDL parsers!

For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet.