mirror of
https://github.com/YosysHQ/sby.git
synced 2025-04-12 16:28:17 +00:00
549c5f33f5
Demonstrate binding SVA properties to a VHDL design. Mention example code (with snippets) in section on Verific.
1 line
13 B
Plaintext
1 line
13 B
Plaintext
formal_bind*/ |