Jannis Harder 6d3b5aa960 Unified trace generation using yosys's sim across all engines ... Currently opt-in using the `fst` or `vcd_sim` options.		2023-01-10 18:42:26 +01:00
..
autotune	Test autotune	2022-06-27 15:58:42 +02:00
junit	Don't fail tests when xmlschema is missing	2022-06-03 17:22:45 +02:00
keepgoing	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
make	tests: Do not run the same SBY task multiple times in parallel	2022-10-20 14:18:51 +02:00
parser	sby: core: Added unsupported messages to the new sections	2022-08-18 05:36:11 -04:00
regression	Fix engine_list's return value	2022-09-15 15:47:27 +02:00
unsorted	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
.gitignore	Refactor tests	2022-04-11 17:50:38 +02:00
Makefile	tests: Windows fixes	2022-07-05 15:34:27 +02:00