mirrors/sby
3
0
Fork 0
mirror of https://github.com/YosysHQ/sby.git synced 2025-04-04 13:54:07 +00:00
Code Activity
274 commits 7 branches 26 tags 1.3 MiB
Python 84.7%
Rust 11.2%
Makefile 1.7%
Verilog 1.1%
SystemVerilog 0.9%
Other 0.4%
Find a file
Claire Xenia Wolf 1b3832cf92 Fixed names and links
2021-10-31 14:42:39 +01:00
docs Fixed names and links 2021-10-31 14:42:39 +01:00
extern Fixed names and links 2021-10-31 14:42:39 +01:00
sbysrc Fixed names and links 2021-10-31 14:42:39 +01:00
tests fix test rule 2020-07-24 16:06:44 +02:00
.gitignore Add aiger engine 2017-02-19 23:53:01 +01:00
COPYING Fixed names and links 2021-10-31 14:42:39 +01:00
Makefile sed -i option is not posix, and argument syntax is incompatible between mac and linux. use redirects instead 2020-10-09 12:04:19 +02:00
README.md Fixed names and links 2021-10-31 14:42:39 +01:00

README.md

SymbiYosys (sby) is a front-end driver program for Yosys-based formal hardware verification flows. See https://yosyshq.readthedocs.io/projects/sby/ for documentation on how to use SymbiYosys.

SymbiYosys (sby) itself is licensed under the ISC license, note that the solvers and other components used by SymbiYosys come with their own license terms. There is some more details in the "Selecting the right engine" section of the documentation.