Formal extensions to Verilog
============================

TBD

``read_verilog -formal``

SystemVerilog Immediate Assertions
----------------------------------

TBD

``assert(<expr>);``

``assume(<expr>);``

``cover(<expr>);``

SystemVerilog Functions
-----------------------

TBD

``$past``

``$stable``

``$rose``, ``$fell``

Liveness and Fairness
---------------------

TBD

``assert(eventually <expr>);``

``assume(eventually <expr>);``

Unconstrained Variables
-----------------------

TBD

Nonstandard Extensions in Yosys
-------------------------------

TBD