[options]
mode bmc
depth 1
expect error

[engines]
smtbmc

[script]
read_verilog -formal test.v
prep -top top

[file test.v]
(* blackbox *)
module submod(a, b);
	input [7:0] a;
	output [7:0] b;
endmodule

module top;
	wire [7:0] a = $anyconst, b;

	submod submod(
		.a(a),
		.b(b)
	);

	always @* begin
		assert(~a == b);
	end
endmodule