[tasks]
abc_bmc3 bmc
abc_sim3 bmc
aiger_avy prove
aiger_suprove prove
abc_pdr prove

[options]
bmc: mode bmc
prove: mode prove
expect fail
wait on

[engines]
abc_bmc3: abc bmc3
abc_sim3: abc sim3
aiger_avy: aiger avy
aiger_suprove: aiger suprove
abc_pdr: abc pdr

[script]
read -sv test.sv
prep -top test

[file test.sv]
module test (
    input clk,
    input [8:1] nonzero_offset
);
    reg [7:0] counter = 0;

    always @(posedge clk) begin
        if (counter == 3) assert(nonzero_offset[1]);
        counter <= counter + 1;
    end
endmodule