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switch to using hierarchy -smtcheck for smtlib2 solvers, allowing smtlib2_module modules.
Fixes: #168 Depends on: https://github.com/YosysHQ/yosys/pull/3391
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41cd8e5b5e
commit
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3 changed files with 69 additions and 6 deletions
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@ -465,7 +465,7 @@ class SbyTask(SbyConfig):
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if not os.path.isdir(f"{self.workdir}/model"):
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os.makedirs(f"{self.workdir}/model")
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def print_common_prep():
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def print_common_prep(check):
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if self.opt_multiclock:
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print("clk2fflogic", file=f)
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else:
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@ -482,7 +482,7 @@ class SbyTask(SbyConfig):
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print("setundef -anyseq", file=f)
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print("opt -keepdc -fast", file=f)
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print("check", file=f)
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print("hierarchy -simcheck", file=f)
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print(f"hierarchy {check}", file=f)
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if model_name == "base":
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with open(f"""{self.workdir}/model/design.ys""", "w") as f:
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@ -490,7 +490,7 @@ class SbyTask(SbyConfig):
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for cmd in self.script:
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print(cmd, file=f)
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# the user must designate a top module in [script]
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print("hierarchy -simcheck", file=f)
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print("hierarchy -smtcheck", file=f)
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print(f"""write_jny -no-connections ../model/design.json""", file=f)
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print(f"""write_rtlil ../model/design.il""", file=f)
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@ -522,7 +522,7 @@ class SbyTask(SbyConfig):
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print("memory_map", file=f)
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else:
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print("memory_nordff", file=f)
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print_common_prep()
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print_common_prep("-smtcheck")
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if "_syn" in model_name:
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print("techmap", file=f)
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print("opt -fast", file=f)
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@ -555,7 +555,7 @@ class SbyTask(SbyConfig):
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print("memory_map", file=f)
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else:
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print("memory_nordff", file=f)
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print_common_prep()
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print_common_prep("-simcheck")
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print("flatten", file=f)
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print("setundef -undriven -anyseq", file=f)
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if "_syn" in model_name:
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@ -587,7 +587,7 @@ class SbyTask(SbyConfig):
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print(f"# running in {self.workdir}/model/", file=f)
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print("read_ilang design.il", file=f)
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print("memory_map", file=f)
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print_common_prep()
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print_common_prep("-simcheck")
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print("flatten", file=f)
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print("setundef -undriven -anyseq", file=f)
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print("setattr -unset keep", file=f)
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