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tristate example

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Matt Venn 2022-06-13 13:51:04 +02:00
parent a200043709
commit b42b6445b8
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docs/examples/tristate/tristates.v Normal file
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`default_nettype none
module module1 (input wire active, output wire tri_out);
assign tri_out = active ? 1'b0 : 1'bz;
endmodule
module module2 (input wire active, output wire tri_out);
assign tri_out = active ? 1'b0 : 1'bz;
endmodule
module top_pass (input wire clk, input wire active1, input wire active2, output wire out);
module1 module1 (.active(active1), .tri_out(out));
module2 module2 (.active(!active1), .tri_out(out));
endmodule
module top_fail (input wire clk, input wire active1, input wire active2, output wire out);
module1 module1 (.active(active1), .tri_out(out));
module2 module2 (.active(active2), .tri_out(out));
endmodule