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Add docs/examples/abstract

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2019-03-27 14:45:30 +01:00
parent f918e2369a
commit afe6960ffe
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docs/examples/abstract/props.sv Normal file
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module demo_props (
input clock, reset,
input A, B, C, D
);
default clocking @(posedge clock); endclocking
default disable iff (reset);
assert property (A |-> !{B,C,D} [*] ##1 B);
assert property (B |-> !{A,C,D} [*] ##1 C);
assert property (C |-> !{A,B,D} [*] ##1 D);
assert property (D |-> !{A,B,C} [*] ##1 A);
cover property (A ##[+] B ##[+] C ##[+] D ##[+] A);
endmodule
bind demo demo_props demo_props_i (.*);