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Add note on docs to clarify verific support

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Having a verific license does not provide access to the verific frontend. This helps to make that clearer.
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Krystine Sherwin 2024-05-14 12:25:29 +12:00
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docs/source/verific.rst
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@ -2,6 +2,14 @@
SystemVerilog, VHDL, SVA
========================
.. note::
This document describes features only available with the commercial `Tabby
CAD Suite`_ and the included Verific frontend. This is not the same as simply
having a Verific license when using Yosys.
.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
Run ``verific -sv <files>`` in the ``[script]`` section of you ``.sby`` file
to read a SystemVerilog source file, and ``verific -vhdl <files>`` to read a
VHDL source file.